CADless laser assisted methodologies for failure analysis and device reliability

Defect isolation and failure analysis is a key factor that drive development and manufacturing yield improvements in semiconductor packaging industry. From a manufacturing point of view, ensuring adequate package reliability is becoming more challenging due to increasing packaging complexity and a more pronounced impact from material physical property mismatch among packaging materials and components. The task of isolating defects and finding root cause is further complicated by ever shrinking feature sizes within the device and/or package, already approaching the nanometer range in contemporary semiconductor packages. Conventional failure analysis techniques such as physical cross sectioning or micro-cutting using focused ion beams(FIB) are sometimes no longer sufficient to find these defects. Both physical cross section and FIB are only capable of exposing the defect in two dimensions (x and y directions), which makes pinpointing the defect in depth, i.e., the z direction, extremely difficult when dealing defects with micron and submicron size. Additional complications are many times introduced during conventional sample preparation, which can introduce undesirable artifacts associated with the module and/or device depackaging. These artifacts may mask the true defects, or lead to misinterpretation of the true cause of failure. In this work, it has been determined that a three-dimensional failure analysis method is critical for finding some defects in silicon packages. For example, xenon difluoride (XeF2) has excellent selectivity to silicon and provides efficient material removal by chemical reaction, generating gaseous by-products that can be readily exhausted [1]. Furthermore, XeF2 has very little reaction with non-silicon materials, such as SiO2, and the metals and polymers commonly used in semiconductor devices and packages. This paper reports the application of XeF2 as an effective failure analysis technique to reveal defects in silicon packages. The mechanism of selective reaction between XeF2 and Si is discussed and key design features of the failure analysis tool are presented. The paper also highlights a few case studies which advantageously utilize XeF2 etching to expose defects. XeF2 was especially effective in detecting the source of electrical leakage in 3D packages having Through Silicon Via (TSV) structures. Due to its high etching selectivity to silicon, the leakage area in electrically failing samples was found to be due to damage of the TSV liner (passivation layer material) and further analysis reveals a three dimensional view of the TSV defect. With the addition of XeF2 etching, further characterization of defects by traditional methods such as FIB micro cutting also becomes more practical. The work suggests that a wider application of Si removal via XeF2 can be achieved by combining mechanical milling of bulk silicon followed by a final, low stress, silicon removal by XeF2 etching.

Failure analysis (FA) is a basic and effective method to obtain the physical and failure information of electronic components and circuits. Most of these information can provide many useful evidences for prognostic and system health management (PHM) of electronic products. To obtain these information, many failure analysis techniques are used. This paper focuses on analyzing the relationship between FA techniques and PHM system. To test and verify the availability of the relationship between FA techniques and PHM system, a failure analysis case of an Intelligent Power Module (IPM) is used to study the relationship. This IPM contains six insulated gate bipolar transistors (IGBTs) and there are obvious burnout indications on most of them after failure. With the process of failure analysis, the key information, such as component's structure, sensitive parameters are identified. These results persuasively prove that FA techniques can provide much information to PHM system, including PoF and data-driven methods.

The electronic components are the core of all electronic products, the reliability and maintainability directly affect manufacture products quality. And as products become more complex and more demanding. We need more reliable components. In order to solve this problem, we need to analysis how and why those components failed. Failure analysis cases are important data for analysis, data mining and improving reliability. China Electronic Product Reliability and Environment Testing Research Institute (CEPREI) is the earliest research organization engaged in reliability research and failure analysis in China, and has accumulated rich failure case data. By combining data mining methods such as Bayesian network, correlation analysis, we can perform statistical analysis and root cause analysis to assist failure analysis and improve product reliability. This paper will apply the failure analysis case of the electromagnetic relay, and explores and analyses related regular pattern.

Root cause failure analysis of lithium-ion batteries provides important feedback for cell design, manufacture, and use. As batteries are being produced with larger form factors and higher energy densities, failure analysis techniques must be adapted to characteristics of the specific batteries. This paper will discuss the significance of melted copper in lithium-ion battery cells that have experienced thermal runaway and how the interpretation of such evidence has evolved over time. Specialized testing techniques that may prove helpful in determining the root cause of battery failures will also be described.

To reduce electricity generation cost, utilities, IPP and industrial users are strongly asking to minimize life cycle time cost and maximize utilization and effective operation of existing power units. To meet these requirements, we replaced the conventional interval-based life management of units with the new risk and condition-based life management to extend the inspection intervals and to shorten inspection periods, and realized the significant improvement in availability and the reduction in maintenance cost. We also clarified the mechanism of aged deterioration of stator and rotor coil insulation, and established the life estimation technology. We furthermore established and put into practical use the wet-beat deterioration life estimation technology for water-cooled stator bars. Regarding the enhancement use of existing units, we improved cooling technology and newly developed HTC (high thermal conductivity) stator insulation system resulting in substantial output increase and efficiency improvement. We have established the technologies for the 2-shift operation. In the early 80s, these technologies were applied to a large-capacity water-cooled unit of DSS operation. This unit is currently running satisfactorily after 20-year operation. It is important, should a failure occur, to immediately reach the root cause of the failure and take the appropriate corrective actions considering economy. It is possible to propose optimal corrections to meet the user needs by using a new failure analysis technique and a new method to evaluate the different approaches to correction. This paper presents a new life management concept and service technologies for turbo-generators.

Failure analysis on 14 nm FinFET devices with ESD CDM failure

Photon Emission Microscopy (PEM) is a popular technique for microelectronics failure analysis by detecting the photon emission from a defective circuit, when a failing device is electrically exercised at certain voltage. The photon emission contains physical location information, photon emission spectral information and photon emission intensity information. People often use the physical location information to localize a defective circuit and guide the follow-up physical failure analysis to find the defects. However, this procedure does not always work. Sometimes, it shows no defect found (NDF). In this paper, we propose a new computer vision-based analysis of the photon emission intensity for identifying the root cause of the excessively high IDDQ at elevated Vdds. The procedure includes collecting photon emissions at different Vdds and a follow-up photon emission intensity analysis with computer vision techniques. The procedure was applied on a case of microprocessor chip. After analyzing the dependencies of photon emission intensity on Vdd for 4 types of circuits, it was concluded that the SRAM circuit leakage is the root cause of the excessively high IDDQ at elevated Vdd.

Detecting failure in electrical connectivity at the component packaging level is a major expenditure of the industry’s failure analysis (FA) resources. These package failures can result from material/manufacturing excursions, stress tests, and/or customer returns. However, many of the methods employed currently (such as X-ray or crosssectioning) can fall short in terms of throughput time, or success rate. Moreover, many FA techniques can be destructive and therefore leave the sample useless for subsequent tests. On the other hand, time domain reflectometry (TDR) can be used as a component packaging level FA tool which meets the needs of quickly, precisely, and non-destructively locating electrical connectivity problems in signal traces. Once the failure location has been pin pointed, other FA methods (X-ray, cross-section, etc.) can be used more easily to determine why the failure occurred. Since TDR testing involves no physical preparation, the sample will be completely intact for subsequent tests. TDR uses a low voltage, low current, and very short rise time voltage pulse to determine the impedance of a signal trace as a function of time. With a waveform of trace impedance versus time, not only can the presence of a failure be detected, but the distance along the trace to the anomaly can also be quickly determined. This paper presents TDR as a useful tool for package level failure analysis labs. The paper proposes one set of solutions for enabling effective TDR analysis (e.g., TDR test fixturing), and discusses some TDR methodologies for detecting and locating anomalies. The methodologies will be illustrated using three example cases that reflect some commonly used packaging technologies: Flip-Chip Organic Land Grid Array (FC-OLGA), Flip-Chip Pin Grid Array (FC-PGA), and Plastic Land Grid Array (PLGA).

The focused ion beam system has been widely used as a critical failure analysis tool as microprocessor technology advances at a ramping speed. It has become an essential step in failure analysis to reveal physical defects after electrical fault isolation. In the highly competitive and challenging environment prevalent at present, failure analysis throughput time is of utmost important. Therefore, a quick, efficient and reliable physical failure analysis technique is needed. This paper discusses the applications of FIB as a defect localization and root cause determination tool through the passive charge contrast technique and pattern FIB analysis.

A novel technique, using infra-red microscopy in the reflection mode, has been used to examine gold-aluminium bond interconnections rapidly by imaging through the bulk silicon. Its use has led to the characterisation of the Au-Al interf ace and the degree of intermetallic formation in terms of a unique IR footprint. The database of footprints obtained from a range of heat-treated commercial product has allowed a good understanding of the bond quality and its possible effect on device reliability. Comparison with results from conventional failure analysis (FA) techniques has demonstrated its use for field failures. The method is eminently suitable as a tool for both qualification and testing exercises and for field failures.

Failure analysis plays an important role in yield improvement during semiconductor process development and device manufacturing. It includes two main steps. The first step is to find the defect and the second step is to identify the root cause. In the past, failure analysis mainly focused on the first step, namely how to find the defect for a failure; because in the previous generations of technology, once the defect was found, its root cause was relatively easy to be understood. As the current advanced semiconductor technology has become tremendously complicated, especially 3D devices, like FinFET, a defect found by failure analysis can be substantially transformed from its original defect by subsequent processes and can be totally different from its origin in size and shape. Thus, sometimes, the second step, identifying the root cause for a defect becomes more challenging and takes more time than the first step. With combination of failure analysis and inline inspection, it enables us to establish the relationship between the failure analysis defect and an in-line defect. This can link the defect for a device functional failure to its source layer and process step more quickly, leading to fast root cause identification. In this paper, the methodology was validated by fast identification of the root causes for three case studies in the latest FinFET technology.

Conventional focussed ion beam (FIB) based specific area transmission electron microscopy (TEM) sample preparation techniques usually requires complex grinding and gluing steps before final FIB thinning of the sample to electron transparency (<0.25 μm). A novel technique known as lift-out, plucking or pullout method that eliminates all the pre-FIB sample preparation has been developed for specific area TEM sample preparation by several authors. The advantages of the lift-out procedure include reduced sample preparation time and possibility of specific area TEM sample preparation of most components of integrated circuit with almost no geometric or dimensional limitations. In this paper, details of liftout method, developed during the present work, for site specific x-sectional and a new site specific planar sample preparation are described. Various methodologies are discussed to maximize the success rate by optimizing the factors that affect the technique. In failure analysis, the geometric and dimensional flexibility offered by the lift-out technique can be used to prepare specific area TEM sample of back thinned die, small particles and packaged parts. Such novel applications of lift-out technique in failure analysis are discussed with the examples of TEM results obtained from GaAs and Si based devices. Importantly, it was possible to obtain high resolution lattice images from the lift-out samples transferred on holey carbon supported 3mm copper grids.

Root Cause Analysis of Product Service Failure Using Computer Experimentation Technique

Guide for authors — Geo-Science Publications

Low power mode current is a very important parameter of most microcontrollers. A non-production prototype microcontroller had high current issues with certain SRAM modules which were produced using a new memory compiler. All devices were measuring 100’s μA of low power mode current which was an order of magnitude higher than the requirement. Many failure analysis (FA) techniques had to be used to determine the root cause: Optical Beam Induced Resistance Change (OBIRCh), photo emission microscopy (PEM), microprobing, and nanoprobe device characterization. Transistor models and measurements of probe structures from the effected lots both predicted that the device low power mode current would meet expectations; however, all first silicon samples had elevated low power mode current. A knowledge of low power design methodology was needed to ensure all issues were discovered.