Guide for authors — Geo-Science Publications

Failure analysis (FA) is a basic and effective method to obtain the physical and failure information of electronic components and circuits. Most of these information can provide many useful evidences for prognostic and system health management (PHM) of electronic products. To obtain these information, many failure analysis techniques are used. This paper focuses on analyzing the relationship between FA techniques and PHM system. To test and verify the availability of the relationship between FA techniques and PHM system, a failure analysis case of an Intelligent Power Module (IPM) is used to study the relationship. This IPM contains six insulated gate bipolar transistors (IGBTs) and there are obvious burnout indications on most of them after failure. With the process of failure analysis, the key information, such as component's structure, sensitive parameters are identified. These results persuasively prove that FA techniques can provide much information to PHM system, including PoF and data-driven methods.

Defect isolation and failure analysis is a key factor that drive development and manufacturing yield improvements in semiconductor packaging industry. From a manufacturing point of view, ensuring adequate package reliability is becoming more challenging due to increasing packaging complexity and a more pronounced impact from material physical property mismatch among packaging materials and components. The task of isolating defects and finding root cause is further complicated by ever shrinking feature sizes within the device and/or package, already approaching the nanometer range in contemporary semiconductor packages. Conventional failure analysis techniques such as physical cross sectioning or micro-cutting using focused ion beams(FIB) are sometimes no longer sufficient to find these defects. Both physical cross section and FIB are only capable of exposing the defect in two dimensions (x and y directions), which makes pinpointing the defect in depth, i.e., the z direction, extremely difficult when dealing defects with micron and submicron size. Additional complications are many times introduced during conventional sample preparation, which can introduce undesirable artifacts associated with the module and/or device depackaging. These artifacts may mask the true defects, or lead to misinterpretation of the true cause of failure. In this work, it has been determined that a three-dimensional failure analysis method is critical for finding some defects in silicon packages. For example, xenon difluoride (XeF2) has excellent selectivity to silicon and provides efficient material removal by chemical reaction, generating gaseous by-products that can be readily exhausted [1]. Furthermore, XeF2 has very little reaction with non-silicon materials, such as SiO2, and the metals and polymers commonly used in semiconductor devices and packages. This paper reports the application of XeF2 as an effective failure analysis technique to reveal defects in silicon packages. The mechanism of selective reaction between XeF2 and Si is discussed and key design features of the failure analysis tool are presented. The paper also highlights a few case studies which advantageously utilize XeF2 etching to expose defects. XeF2 was especially effective in detecting the source of electrical leakage in 3D packages having Through Silicon Via (TSV) structures. Due to its high etching selectivity to silicon, the leakage area in electrically failing samples was found to be due to damage of the TSV liner (passivation layer material) and further analysis reveals a three dimensional view of the TSV defect. With the addition of XeF2 etching, further characterization of defects by traditional methods such as FIB micro cutting also becomes more practical. The work suggests that a wider application of Si removal via XeF2 can be achieved by combining mechanical milling of bulk silicon followed by a final, low stress, silicon removal by XeF2 etching.

Book review

Detecting failure in electrical connectivity at the component packaging level is a major expenditure of the industry’s failure analysis (FA) resources. These package failures can result from material/manufacturing excursions, stress tests, and/or customer returns. However, many of the methods employed currently (such as X-ray or crosssectioning) can fall short in terms of throughput time, or success rate. Moreover, many FA techniques can be destructive and therefore leave the sample useless for subsequent tests. On the other hand, time domain reflectometry (TDR) can be used as a component packaging level FA tool which meets the needs of quickly, precisely, and non-destructively locating electrical connectivity problems in signal traces. Once the failure location has been pin pointed, other FA methods (X-ray, cross-section, etc.) can be used more easily to determine why the failure occurred. Since TDR testing involves no physical preparation, the sample will be completely intact for subsequent tests. TDR uses a low voltage, low current, and very short rise time voltage pulse to determine the impedance of a signal trace as a function of time. With a waveform of trace impedance versus time, not only can the presence of a failure be detected, but the distance along the trace to the anomaly can also be quickly determined. This paper presents TDR as a useful tool for package level failure analysis labs. The paper proposes one set of solutions for enabling effective TDR analysis (e.g., TDR test fixturing), and discusses some TDR methodologies for detecting and locating anomalies. The methodologies will be illustrated using three example cases that reflect some commonly used packaging technologies: Flip-Chip Organic Land Grid Array (FC-OLGA), Flip-Chip Pin Grid Array (FC-PGA), and Plastic Land Grid Array (PLGA).

This paper describes a new technique, called the Light-Induced State Transition (LIST) method that uses an optical beam induced current (OBIC) system for failure analysis of CMOS LSIs. This technique allows one to locate a low signal line short-circuited to a GND bus (or a high signal line short-circuited to a V/sub DD/ bus) in stand-by condition which is not possible with conventional failure analysis techniques such as photo-emission analysis, liquid crystal technique, or the conventional OBIC method. The effectiveness of the LIST method was verified by an experiment on inverter chains that included quasi-failures intentionally patched by FIB deposition. The LIST method has also been used for actual CMOS logic failure analysis, and has proved to be useful for finding a failure location rapidly.

Conventional focussed ion beam (FIB) based specific area transmission electron microscopy (TEM) sample preparation techniques usually requires complex grinding and gluing steps before final FIB thinning of the sample to electron transparency (<0.25 μm). A novel technique known as lift-out, plucking or pullout method that eliminates all the pre-FIB sample preparation has been developed for specific area TEM sample preparation by several authors. The advantages of the lift-out procedure include reduced sample preparation time and possibility of specific area TEM sample preparation of most components of integrated circuit with almost no geometric or dimensional limitations. In this paper, details of liftout method, developed during the present work, for site specific x-sectional and a new site specific planar sample preparation are described. Various methodologies are discussed to maximize the success rate by optimizing the factors that affect the technique. In failure analysis, the geometric and dimensional flexibility offered by the lift-out technique can be used to prepare specific area TEM sample of back thinned die, small particles and packaged parts. Such novel applications of lift-out technique in failure analysis are discussed with the examples of TEM results obtained from GaAs and Si based devices. Importantly, it was possible to obtain high resolution lattice images from the lift-out samples transferred on holey carbon supported 3mm copper grids.

Failure analysis on 14 nm FinFET devices with ESD CDM failure

TrenchMOS FET devices fabricated vertically instead of conventional horizontal POWERMOS devices. Conventional failure analysis techniques have shown difficulty in identifying the failing location if the defect happens at the bottom of trench. Different failure analysis techniques have been developed to analyze the low yield wafers. This paper demonstrates the use of various failure analysis techniques to isolate the defective location and assisting Fab process team to resolve the issue and improve yield.

Focused ion beam (FIB) is commonly used as a standard machining technique in failure analysis, quality control, reverse engineering, material research, and so on, for the samples having microstructures and nanostructures. FIB combined with time‐of‐flight secondary ion mass spectrometry (TOF‐SIMS), so‐called FIB‐TOF, has attracted attention as a method to determine the three‐dimensional (3D) chemical distributions of complex samples. In general, a highly focused Ga + ion beam is used for FIB, however, the FIB‐milled area is limited and it was difficult to expand the Ga‐FIB to hundreds of micron length scale for sample fabrication. In order to overcome the drawback, we proposed the Bi‐FIB approach for large scale sample cross‐sectioning. Although the possibility of Bi‐FIB has been reported, there were almost no performance examinations as well as practical applications. In this study, therefore, the authors summarize the comparison of milling rate and milling damage between Ga‐FIB and Bi‐FIB. As a result, it was found that Bi‐FIB can provide a higher milling rate with thinner milling damage. Finally, the Bi‐FIB approach was applied to the interfacial analysis of all‐solid‐state battery (ASSB) material. With this approach, the detailed chemical distributions at the interface were discovered, leading to the better understanding of battery behaviors.

The greatest concern on MOB devices is the physical integrity of the gate oxide. Leakage paths and/or shorts through defect sites in the oxide are a major device reliability problem. Optical microscopy is tedious and often does not resolve the defects. With this in mind, copper decoration techniques were developed that could reveal oxide failures sites down to 0.1?m size. The technique has isolated various failure mechanisms on MOS devices. This failure analysis capability has enhanced the ability to control the MOS process.

X-ray radiographic techniques in failure analysis : L. Jones. Proc. IEEE Reliab. Phys. Symp., 152 (1982)

Fault detection of a sandwich system with dead-zone based on robust observer

Results of calculation seismic resistance analysis of light equipment of nuclear power plants performed on the example of a ventilation unit using two most common analytical techniques - linear spectral analysis and direct dynamic methods - are discussed. The basic concepts, assumptions and limitations of the linear spectral method are described. Examples are given of specific calculation cases when the method in question is not applicable in the generally accepted formulation. In particular, the phase difference and, possibly, accelerations (displacements) must be taken into consideration in the calculations of extended spatial structures for mutually remote boundary conditions. Another example are the reservoirs not completely filled with liquids. In such case waves may be formed in the liquid and taking them into account is not possible in the linear spectral method. Specific features are examined of application of the dynamic analysis method including the input data, approaches and methodologies required for synthesizing the calculated accelerograms. A sequence of operations performed during synthesizing calculated accelerograms is provided, materials are provided containing the description of the mathematical apparatus applied for deriving the final mathematical relations for calculating response spectra and the calculation relations as such are given. The concept of the damping coefficient is explained, its influence on the calculated results and the approaches to its determination are demonstrated. Options with complete absence of damping and with absolute damping are discussed. A real ventilation set applied in active ventilation systems of nuclear power plants was accepted as the test model. Results calculated for the detailed finite-element model of the ventilation unit using the Zenith-95 software package are presented. These results include the distribution of the calculated reduced stresses. Analysis of the results obtained using the two methods demonstrated overestimation of calculated results by the linear spectral method as compared to those obtained by the dynamic analysis method, which means that the former method underestimates the equipment’s resistance to seismic effects. In addition, the dynamic method shows additional areas in the ventilation unit where significant reduced stresses are found while the linear spectral method ignores these areas.

Failure analysis (FA) plays an important role in semiconductor industry as the process technology and new packaging are continuously improved. Fault localization is a key step to narrow down the area of failed part and isolate the defective areas, which is prior to destructive failure analysis. This paper will cover some advanced fault localization techniques and tools in package and die/device level failure analysis. Case studies for those techniques will provide a good understanding and illustrate the applications.

The essential issue in the development of integrated circuit (IC) technologies that allow the arrangement of high densities of electronic components on a single substrate (very‐large‐scale integration technology) is the capability of making a reliable product in a reliable process. To maximize product yield and reliability, modern IC technology requires the availability of a broad range of analytical techniques: on the one hand, techniques that provide fast feed‐back to the process to improve control of the parameters (process monitoring); on the other hand, techniques that allow accruate analysis of failed products (failure analysis). In this contribution the importance of diagnostic techniques for failure analysis will be demonstrated by means of some typical case studies. These include non‐destructive investigations (scanning acoustic tomography) to study the effect of poor adhesion between chip and encapsulant and to study the bonding quality. Furthermore, dendrite‐like structures on the decapsulated chip have been identified with scanning electron microscopy (SEM) and energy dispersive x‐ray analysis (EDXA). In addition, an example will be included that shows the limitations of the performance of the present‐day analytical techniques. The conclusions are: the availability of a large variety of powerful analytical techniques is essential for the development of advanced IC technologies; as a result of the reduction in physical size of the structures on an IC, the limits of performance (in particular, the product of spatial resolution and detection limits) of the present‐day analytical techniques is being approached; there is an increasing need, stimulated by high costs of analysis and required fast feedback of the results, for ‘non‐destructive’ diagnostic techniques.