Advanced fault localization techniques in microelectronics failure analysis

Detecting failure in electrical connectivity at the component packaging level is a major expenditure of the industry’s failure analysis (FA) resources. These package failures can result from material/manufacturing excursions, stress tests, and/or customer returns. However, many of the methods employed currently (such as X-ray or crosssectioning) can fall short in terms of throughput time, or success rate. Moreover, many FA techniques can be destructive and therefore leave the sample useless for subsequent tests. On the other hand, time domain reflectometry (TDR) can be used as a component packaging level FA tool which meets the needs of quickly, precisely, and non-destructively locating electrical connectivity problems in signal traces. Once the failure location has been pin pointed, other FA methods (X-ray, cross-section, etc.) can be used more easily to determine why the failure occurred. Since TDR testing involves no physical preparation, the sample will be completely intact for subsequent tests. TDR uses a low voltage, low current, and very short rise time voltage pulse to determine the impedance of a signal trace as a function of time. With a waveform of trace impedance versus time, not only can the presence of a failure be detected, but the distance along the trace to the anomaly can also be quickly determined. This paper presents TDR as a useful tool for package level failure analysis labs. The paper proposes one set of solutions for enabling effective TDR analysis (e.g., TDR test fixturing), and discusses some TDR methodologies for detecting and locating anomalies. The methodologies will be illustrated using three example cases that reflect some commonly used packaging technologies: Flip-Chip Organic Land Grid Array (FC-OLGA), Flip-Chip Pin Grid Array (FC-PGA), and Plastic Land Grid Array (PLGA).

Failure analysis on 14 nm FinFET devices with ESD CDM failure

Failure analysis (FA) is a basic and effective method to obtain the physical and failure information of electronic components and circuits. Most of these information can provide many useful evidences for prognostic and system health management (PHM) of electronic products. To obtain these information, many failure analysis techniques are used. This paper focuses on analyzing the relationship between FA techniques and PHM system. To test and verify the availability of the relationship between FA techniques and PHM system, a failure analysis case of an Intelligent Power Module (IPM) is used to study the relationship. This IPM contains six insulated gate bipolar transistors (IGBTs) and there are obvious burnout indications on most of them after failure. With the process of failure analysis, the key information, such as component's structure, sensitive parameters are identified. These results persuasively prove that FA techniques can provide much information to PHM system, including PoF and data-driven methods.

Due to the complexity of software systems, bugs are inevitable. Software debugging is tedious and time consuming. To help developers perform this crucial task, a number of spectra-based fault localization techniques have been proposed. In general, spectra-based fault localization helps developers to find the location of a bug given its symptoms (e.g., program failures). A previous study by Parnin and Orso however implies that several assumptions made by existing work on spectra-based fault localization do not hold in practice, which hinders the practical usage of these tools. Moreover, a recent study by Xie et al. claims that spectra-based fault localization can potentially weaken programmers' abilities in fault detection.Unfortunately, these studies are performed either using only 2 bugs from small systems (Parnin and Orso's study) or synthetic bugs injected into toy programs (Xie et al.'s study), only involve students, and use dated spectra-based fault localization tools. Thus, the question whether spectra-based fault localization techniques can help professionals to improve their debugging efficiency in a reasonably large project is still insufficiently answered. In this paper, we perform a more realistic investigation of how professionals can use and benefit from spectra-based fault localization techniques. We perform a user study of spectra-based fault localization with a total of 16 real bugs from 4 reasonably large open-source projects, with 36 professionals, amounting to 80 recorded debugging hours. The 36 professionals are divided into 3 groups, i.e., those that use an accurate fault localization tool, use a mediocre fault localization tool, and do not use any fault localization tool. Our study finds that both the accurate and mediocre spectra-based fault localization tools can help professionals to save their debugging time, and the improvements are statistically significant and substantial. We also discuss implications of our findings to future directions of spectra-based fault localization.

Defect isolation and failure analysis is a key factor that drive development and manufacturing yield improvements in semiconductor packaging industry. From a manufacturing point of view, ensuring adequate package reliability is becoming more challenging due to increasing packaging complexity and a more pronounced impact from material physical property mismatch among packaging materials and components. The task of isolating defects and finding root cause is further complicated by ever shrinking feature sizes within the device and/or package, already approaching the nanometer range in contemporary semiconductor packages. Conventional failure analysis techniques such as physical cross sectioning or micro-cutting using focused ion beams(FIB) are sometimes no longer sufficient to find these defects. Both physical cross section and FIB are only capable of exposing the defect in two dimensions (x and y directions), which makes pinpointing the defect in depth, i.e., the z direction, extremely difficult when dealing defects with micron and submicron size. Additional complications are many times introduced during conventional sample preparation, which can introduce undesirable artifacts associated with the module and/or device depackaging. These artifacts may mask the true defects, or lead to misinterpretation of the true cause of failure. In this work, it has been determined that a three-dimensional failure analysis method is critical for finding some defects in silicon packages. For example, xenon difluoride (XeF2) has excellent selectivity to silicon and provides efficient material removal by chemical reaction, generating gaseous by-products that can be readily exhausted [1]. Furthermore, XeF2 has very little reaction with non-silicon materials, such as SiO2, and the metals and polymers commonly used in semiconductor devices and packages. This paper reports the application of XeF2 as an effective failure analysis technique to reveal defects in silicon packages. The mechanism of selective reaction between XeF2 and Si is discussed and key design features of the failure analysis tool are presented. The paper also highlights a few case studies which advantageously utilize XeF2 etching to expose defects. XeF2 was especially effective in detecting the source of electrical leakage in 3D packages having Through Silicon Via (TSV) structures. Due to its high etching selectivity to silicon, the leakage area in electrically failing samples was found to be due to damage of the TSV liner (passivation layer material) and further analysis reveals a three dimensional view of the TSV defect. With the addition of XeF2 etching, further characterization of defects by traditional methods such as FIB micro cutting also becomes more practical. The work suggests that a wider application of Si removal via XeF2 can be achieved by combining mechanical milling of bulk silicon followed by a final, low stress, silicon removal by XeF2 etching.

Conventional focussed ion beam (FIB) based specific area transmission electron microscopy (TEM) sample preparation techniques usually requires complex grinding and gluing steps before final FIB thinning of the sample to electron transparency (<0.25 μm). A novel technique known as lift-out, plucking or pullout method that eliminates all the pre-FIB sample preparation has been developed for specific area TEM sample preparation by several authors. The advantages of the lift-out procedure include reduced sample preparation time and possibility of specific area TEM sample preparation of most components of integrated circuit with almost no geometric or dimensional limitations. In this paper, details of liftout method, developed during the present work, for site specific x-sectional and a new site specific planar sample preparation are described. Various methodologies are discussed to maximize the success rate by optimizing the factors that affect the technique. In failure analysis, the geometric and dimensional flexibility offered by the lift-out technique can be used to prepare specific area TEM sample of back thinned die, small particles and packaged parts. Such novel applications of lift-out technique in failure analysis are discussed with the examples of TEM results obtained from GaAs and Si based devices. Importantly, it was possible to obtain high resolution lattice images from the lift-out samples transferred on holey carbon supported 3mm copper grids.

The advances on IC technology have made defect localization extremely challenging. “Soft” failures (resistive vias and contacts) are typically difficult to localize using commonly available failure analysis (FA) techniques such as emission microscopy (EMMI) and scanning optical microscopy (SOM), and often cannot be observed by two-dimensional inspections using layer by layer removal. The article describes the Resistive Contrast Imaging (RCI) defect localization technique (also known as Electron Beam Absorbed Current (EBAC), instrumentations, and case studies on test structures or process control monitors especially designed to detect “soft” open failures on advanced (28nm and below) technology devices. It also lists the key SEM parameters critical for effective FA using the RCI nano-probing system.

Photon Emission Microscopy (PEM) is a popular technique for microelectronics failure analysis by detecting the photon emission from a defective circuit, when a failing device is electrically exercised at certain voltage. The photon emission contains physical location information, photon emission spectral information and photon emission intensity information. People often use the physical location information to localize a defective circuit and guide the follow-up physical failure analysis to find the defects. However, this procedure does not always work. Sometimes, it shows no defect found (NDF). In this paper, we propose a new computer vision-based analysis of the photon emission intensity for identifying the root cause of the excessively high IDDQ at elevated Vdds. The procedure includes collecting photon emissions at different Vdds and a follow-up photon emission intensity analysis with computer vision techniques. The procedure was applied on a case of microprocessor chip. After analyzing the dependencies of photon emission intensity on Vdd for 4 types of circuits, it was concluded that the SRAM circuit leakage is the root cause of the excessively high IDDQ at elevated Vdd.

This paper describes a new technique, called the Light-Induced State Transition (LIST) method that uses an optical beam induced current (OBIC) system for failure analysis of CMOS LSIs. This technique allows one to locate a low signal line short-circuited to a GND bus (or a high signal line short-circuited to a V/sub DD/ bus) in stand-by condition which is not possible with conventional failure analysis techniques such as photo-emission analysis, liquid crystal technique, or the conventional OBIC method. The effectiveness of the LIST method was verified by an experiment on inverter chains that included quasi-failures intentionally patched by FIB deposition. The LIST method has also been used for actual CMOS logic failure analysis, and has proved to be useful for finding a failure location rapidly.

Guide for authors — Geo-Science Publications

Focused ion beam (FIB) is commonly used as a standard machining technique in failure analysis, quality control, reverse engineering, material research, and so on, for the samples having microstructures and nanostructures. FIB combined with time‐of‐flight secondary ion mass spectrometry (TOF‐SIMS), so‐called FIB‐TOF, has attracted attention as a method to determine the three‐dimensional (3D) chemical distributions of complex samples. In general, a highly focused Ga + ion beam is used for FIB, however, the FIB‐milled area is limited and it was difficult to expand the Ga‐FIB to hundreds of micron length scale for sample fabrication. In order to overcome the drawback, we proposed the Bi‐FIB approach for large scale sample cross‐sectioning. Although the possibility of Bi‐FIB has been reported, there were almost no performance examinations as well as practical applications. In this study, therefore, the authors summarize the comparison of milling rate and milling damage between Ga‐FIB and Bi‐FIB. As a result, it was found that Bi‐FIB can provide a higher milling rate with thinner milling damage. Finally, the Bi‐FIB approach was applied to the interfacial analysis of all‐solid‐state battery (ASSB) material. With this approach, the detailed chemical distributions at the interface were discovered, leading to the better understanding of battery behaviors.

The greatest concern on MOB devices is the physical integrity of the gate oxide. Leakage paths and/or shorts through defect sites in the oxide are a major device reliability problem. Optical microscopy is tedious and often does not resolve the defects. With this in mind, copper decoration techniques were developed that could reveal oxide failures sites down to 0.1?m size. The technique has isolated various failure mechanisms on MOS devices. This failure analysis capability has enhanced the ability to control the MOS process.

X-ray radiographic techniques in failure analysis : L. Jones. Proc. IEEE Reliab. Phys. Symp., 152 (1982)

Laser assisted device alteration (LADA) is a laser-based technique to verify device under test and has been widely used for soft failure debugging. This technique requires the device to be scanned with a laser while it is under active stimulation by the tester. By monitoring test results and scanning laser position, it gives the location of defect and critical path. In the case of complex logic failures in advanced technology nodes, defect localization continues to be a challenge in the failure analysis field. Dynamic electrical failure analysis (D-EFA) techniques and their derivatives can increase efficiency for defect localization techniques. In this paper, several soft failure case studies will be demonstrated by using LADA techniques and further nano-probing results will also be described by physical failure analysis (PFA).

TrenchMOS FET devices fabricated vertically instead of conventional horizontal POWERMOS devices. Conventional failure analysis techniques have shown difficulty in identifying the failing location if the defect happens at the bottom of trench. Different failure analysis techniques have been developed to analyze the low yield wafers. This paper demonstrates the use of various failure analysis techniques to isolate the defective location and assisting Fab process team to resolve the issue and improve yield.