Laser Assisted Device Alteration, Efficient Application for Soft Failure Localization on Advanced Node

Pulsed-LADA is found to play an important role in the advancement of next-generation LADA and it is reported that tens of μs pulses with 10 kHz frequency is sufficient to observe enhancements in carrier injection. Electrically-enhanced LADA (EeLADA), based on pulsed-LADA, is introduced as a new fault localization method capable to overcome current limitation of Laser Assisted Device Alteration (LADA) application on soft failure and extends it to hard failure debug. We present the EeLADA methodology and experimental data to demonstrate its feasibility.

As semiconductor manufacturing progresses to smaller process nodes, it is becoming increasingly difficult to climb the yield learning curve rapidly. The rate of yield learning dictates the growth and success of the semiconductor industry, and must be accelerated to fulfill competitive time-to-market, time-to-money and time-to-volume requirements. Software-based diagnosis plays a crucial role in yield learning. Diagnosis comprehends the test response of a failing circuit to determine the location, and sometimes, in addition, characterize the nature of a defect affecting the failing circuit. Besides identifying likely failure mechanisms and increasing the quality of chip testing, the feedback provided by diagnosis is used to select chips for physical failure analysis (PFA). PFA aims to visually examine a chip to characterize a defect, prevent similar defects in the future and, consequently, improve the design and manufacturing of a chip.However, PFA is often destructive, time- and cost-intensive, and not always successful. Diagnosis, on the other hand, is non-invasive and time- and cost-effective; moreover, it assists PFA and guides yield learning. The advantages of diagnosis, coupled with the diminishing performance of PFA with advancing technology, make it an encouraging facilitator for rapid yield learning.Therefore, the objective of diagnosis must be logic-level defect characterization to minimize (and ideally eliminate) the need for PFA, and accelerate yield learning. Logic characterization of a defect includes the derivation of its physical location and precise logic behavior. In this dissertation, a comprehensive diagnosis methodology is developed to actualize the aforementioned objective.The developed methodology comprises of three methods. LearnX/MD-LearnX is a physically-aware method that employs (a) the X-fault model to avert the elimination of a correct defect candidate and (b) machine learning to build a candidate-ranking model that learns the hidden correlations between the tester response and the defect candidates to pinpoint the correct candidate. PADLOC, which stands for Physically-Aware Defect LOcalization and Characterization, improves the physical location of a back-end defect (i.e., a defect that affects one or more interconnects and resides outside a standard cell) returned by LearnX/MD-LearnX by partitioning the defective net into physical subnets and identifying the subnets that influence defect excitation. In addition, PADLOC deduces the precise impact of a defect on the circuit functionality by examining its surrounding circuitry. NOIDA, which stands for NOise-resistant Intra-cell Diagnosis Approach, pinpoints the location of a defect within a failing standard cell implicated by LearnX/MD-LearnX. In contrast to prior work that typically constructs/employs a fault dictionary, NOIDA ascertains the location as well as the behavior of a front-end defect (i.e., a defect that resides inside a standard cell) by monitoring the logical activity of its intra-cell neighborhood. Additionally, NOIDA is resistant to circuit-level noise that may originate from potentially inaccurate transistor-level simulation. Results from numerous experiments reveal that our diagnosis methodology outperforms state-of-the-art commercial diagnosis. LearnX/MD-LearnX reports fewer defect candidates than commercial diagnosis for 69.4% silicon fail logs without losing accuracy. PADLOC implicates a smaller physical area for a defect for 47.2% silicon fail logs and attains at most 44X improvement. NOIDA reports an ideal diagnosis for 38.0% more front-end defects, when compared to leading-edge commercial diagnosis. In the presence of noise, NOIDA achieves an ideal diagnosis 7.6X more often.In summary, this dissertation endeavors to characterize a defect residing in a logic chip in terms of its precise physical location and logic behavior, which, consequently, most likely, enables rapid yield learning. The deployment of machine learning to pinpoint the correct candidate in LearnX/MD-LearnX, and the investigation of the neighborhood of a defect to determine its exact physical location and logic behavior in PADLOC and NOIDA are the novel components of this dissertation, and the reasons for its superiority over the state-of-the-art.

It has been long recognized that SRAM memory is an ideal vehicle for defect monitoring and yield improvement during process development because of its highly structured architecture and simplified approach using memory bitmapping. However, the success rate of defect detection, especially for soft single-column failures, which is one of the most complex failure modes of an SRAM failure, is decreasing when using traditional physical failure analysis (PFA) with only the bitmap available for guidance due to a variety of invisible or undetectable defects that cause a leakage behavior in the device. In order to understand the leakage behavior in advanced high voltage (HV) processes, conductive atomic force microscope (C-AFM) [1-5] is introduced to perform junction-level fault isolation prior to attempting PFA. In this study, the quantified data extracted using the C-AFM can also be used to establish a connection between the failure mechanism discovered and the soft single column failure mode.

Fault Isolation / Failure Analysis (FI/FA) of increasingly complex embedded memory in microprocessors is becoming more difficult due to process scaling and presence of subtle defects. As physical failure analysis (PFA) is destructive and involves expensive and time-consuming processes, fault diagnosis needs to be as precise as possible to ensure successful physical defect sighting. This paper introduces a cache Fault Isolation methodology that focuses on exhaustive data collection to derive concrete hypothesis of physical fault location and to overcome the existing FA/FI challenges. The methodology involves a novel application of existing DFT techniques in combination with circuit analysis, pattern hacking, defect localization and PFA tools. Some of the techniques, for example pattern modification or circuit simulation, are applied repeatedly in order to obtain higher-level of isolation – from cell/logic level to transistor/gate level, and finally down to physical structure/layer level. This multi-level FI approach is the key to localize the failing area to greater precision, which had proven itself in Intel Itanium® II processor yield improvement process.

Optoelectronic imaging of integrated-circuits has revolutionized device design debug, failure analysis and electrical fault isolation; however modern probing techniques like laser-assisted device alteration (LADA) have failed to keep pace with the semiconductor industry's aggressive device scaling, meaning that previously satisfactory techniques no longer exhibit a sufficient ability to localize electrical faults, instead casting suspicion upon dozens of potential root-cause transistors. Here, we introduce a new high-resolution probing technique, two-photon laser-assisted device alteration (2pLADA), which exploits two-photon absorption (TPA) to provide precise three-dimensional localization of the photo-carriers injected by the TPA process, enabling us to implicate individual transistors separated by 100 nm. Furthermore, we illustrate the technique's capability to reveal speed-limiting transistor switching evolution with an unprecedented timing resolution approaching <10 ps. Together, the exceptional spatial and temporal resolutions demonstrated here now make it possible to extend optical fault localization to sub-14 nm technology nodes.

This paper describes the integrated fast failure analysis/yield enhancement system used at Motorola's MOS-12 fab, established with the goal of providing high speed diagnostics and feedback. This goal was achieved through tight integration of in-fab inspection tools with electrical test equipment, out-of-fab analytical tools, and software tools. At this facility, the use of common file formats permits data exchange between wafer inspection tools, optical review stations, SEM, FIB, and electrical work bench testers. Wafer images generated at all diagnostic tools are stored on a video archival/retrieval system (VARS<SUP>TM</SUP>). Correlation is a powerful tool for reducing failure analysis time and increasing failure analysis efficiency. By overlaying in-line inspection data with process, parametric, sort bin, and bitmap data, the locations of potential killer defects are rapidly identified. Physical failure analysis is performed on selected correlated failures to confirm the cause of device failures. Using analytical instruments with full wafer capability, in-line inspection or bitmap information are used to quickly locate the defects of interest. This approach has been successfully used to significantly reduce FA time compared with traditional FA methods. Fast failure analysis/yield enhancement is demonstrated with three case studies.

Laser Voltage Imaging (LVI) has become a well-established method for isolating scan-shift (i.e., scan chain integrity) tests failures [1, 2]. When LVI is coupled with time-domain information acquired using Continuous-Wave Laser Voltage Probing (CW-LVP) [3], the Physical Failure Analysis (PFA) success rate exceeds 90% for all types of failing conditions, from hard stuck-at fails to soft transition fails. This combination of Electrical Failure Analysis (EFA) techniques is effective because of its ability to pre-isolate the defect to a small enough area for successful PFA. While high PFA success rates are proven, there remains the issue of throughput: CW-LVP can be time consuming, and techniques that minimize the need for it are important. This paper introduces a novel LVI methodology that incorporates phase information [4] and reduces the need for CW-LVP for certain types of failures. Case studies will be presented.

Integrated capacitors use metal plates such as in Metal-Insulator-Metal (MIM) and Metal-Oxide-Metal (MOM) capacitors while Polysilicon and Silicon (Si) substrate for metal-oxide-semiconductor (MOS) capacitors. Three major challenges and solutions were discussed in this technical paper. First, the failure site localization of a subtle defect in the capacitor plates. To determine the specific location of the defect site, Electron Beam Induced Current (EBIC) analysis was performed while the part was biased using a nano-probe set-up under Scanning Electron Microscopy (SEM) environment. Second, Failure Mechanism contentions between Electrically Induced Physical Damage (EIPD) or Fabrication process defect particularly, for damage site that is not at the edge of the capacitor and without obvious manifestations of Fabrication process anomalies such as bulging, void, unetched material or shifts in the planarity of the die layers. To further understand the defect site, Scanning Transmission Electron Microscopy (STEM) coupled with Energy-Dispersive X-ray Spectroscopy (EDS) were utilized to obtain high magnification imaging and elemental area mapping. Third, misled conclusion to be an EIPD site manifested by burnt and reflowed metallization. The EIPD site was only a secondary effect of a capacitor dielectric breakdown. This has been uncovered after understanding the circuit connectivity, inspections of the capacitors connected to the EIPD site, fault isolation and further physical failure analysis were performed. As results of the Failure Analysis (FA), Customer and Analog Devices Incorporated (ADI) manufacturing hold lots were accurately dispositioned and related corrective actions were precisely identified and implemented.

An application-specific integrated circuit (ASIC) for a high reliability application is found to have a missing sidewall spacer in a single transistor. Manufacturer burn-in and standard component electrical tests do not capture this defect. The defect manifests after exposure to ionizing radiation. Photon emission microscopy (PEM), laser voltage imaging (LVI), and laserassisted device alteration (LADA) are used to isolate the failure site. At the failure site a focused ion beam (FIB) cross section indicates that a doubly doped drain (DDD) (N+) is likely present where a lightly doped drain (LDD) is designated. This defect leads to a failure mode that is consistent with hot-carrier injection in complementary metal-oxide semiconductor (CMOS) transistors. This paper presents the testability from a fault isolation aspect, shmoo plot characterization, and backside optical techniques to identify its spatial location. A discussion of the results includes why ionizing radiation allowed the defect’s capture and potential implications of using ionizing radiation as a viable failure analysis technique.

Thermal Laser Stimulation (TLS) is employed extensively in semiconductor device fault isolation techniques such as TIVA (Thermal Induced Voltage Alteration), OBIRCH (Optical Beam Induced Resistance Change), SDL (Soft Defect localization), CPA (Critical Parameter Analysis), LADA (Laser Assisted Device Alteration), and LVI (Laser Voltage Imaging), etc. To investigate the TLS effects on 7nm FinFET transistor parameters, several transistors of 7nm FinFET inline ET (Electrical Test) macros were tested while employing TLS of various energy values. The test was done in linear mode so that the joule heating caused by the electrical current would be minimized. The experimental results showed that both NFETs and PFETs experienced increased Ioff (Off current) and Sub_Vt_lin_slope (Subthreshold slope), and decreased Ion (On current) and Vt_lin (Threshold voltage) due to elevated temperature of the transistor from TLS. Higher laser power caused greater effects on transistor parameters. The temperature increase on a transistor by TLS depends on the amount of laser energy transferred to, absorbed by, and dispersed by the transistor area. Factors such as the efficient coupling of the SIL (Solid Immersion Lens) with the Silicon backside surface, the transistor size, and the local layout around the transistor will greatly affect the amount of heat delivered to a particular transistor, even while using the same laser power. Thus, setting the laser power for fault isolation with TLS should consider these factors. Our experimental results also showed that the alteration of transistor parameters under TLS was not permanent if the laser power was carefully selected. It should be noticed that during dynamic fault isolation, a transistor may be switching between off, linear mode, and/or saturation mode. The temperature increase on the transistor under TLS may be higher than anticipated due to joule heating if the transistor operation is not confined to the linear region only. Experiments on transistors operating in saturation mode under TLS can be the subject of future work. The results obtained from these experiments can still establish guidelines for laser power settings to be used in the related fault isolation techniques for devices manufactured at the 7nm node so as to achieve non-destructive fault isolation.

The focused ion beam system has been widely used as a critical failure analysis tool as microprocessor technology advances at a ramping speed. It has become an essential step in failure analysis to reveal physical defects after electrical fault isolation. In the highly competitive and challenging environment prevalent at present, failure analysis throughput time is of utmost important. Therefore, a quick, efficient and reliable physical failure analysis technique is needed. This paper discusses the applications of FIB as a defect localization and root cause determination tool through the passive charge contrast technique and pattern FIB analysis.

Focused ion beam system has been widely used as a critical failure analysis tool as microprocessor technology advances at a ramping speed. It has become an essential step in failure analysis to reveal physical defects post electrical fault isolation. In this highly competitive and challenging environment prevalent today, failure analysis throughput time is of utmost important. Therefore quick, efficient and reliable physical failure analysis technique is needed to avoid potential issues from becoming bigger. This paper will discuss the applications of FIB as a defect localization and root cause determination tool through the passive charge contrast technique and pattern FIB analysis.

Current need to the development of advanced 28nm and beyond OTP (One-time-Programmable) nonvolatile memory is limited by the compatibility with advanced nodes with particular high-k metal-gate gate stack feature. On the other hand, there is a strong demand for future use in IoT and AI in security applications. In this talk, we will provide a solution on how to develop a unique structure of OTP for the above purpose. A 4kb macro of One Time Programming (OTP) memory, implemented by a new breakdown, named dielectric fuse (dFuse) breakdown, will be demonstrated which is constructed on a foundry pure logic 28nm HKMG CMOS platform. The feature size of a unit cell is 1.5T per cell with 7.5F2. The experimental results show that dFuse macro exhibits high programming (PGM) speed of 100ns at 4V, read time smaller than 10ns at 0.75V, and excellent data retention under one-month baking at 150°C. More importantly, the program voltage is weakly dependent on the environmental temperature, suitable for automotive applications. This OTP is also expected to be scalable to advanced technology node such as FinFET and provides an ideal and reliable solution for the storage purpose in IoT and 5G era. In particular, it has great potential for embedded applications in MCU, e.g., automotive applications.

Thermal compression bonding is being widely used for fine pitch copper pillar assembly as it provides high die placement accuracy and bonding suitable for mass production. In the current work, chip package interaction induced ILD integrity failures under thermo-compression assembly induced stresses were investigated. A step by step EFA (Electrical Failure Analysis) plus PFA (Physical Failure Analysis) methodology was developed to isolate the failing location and confirm the fail mode. The key steps include initially dataloging the fails and running the data through ATPG (Automatic Test Pattern Generation) tools to localize the failing nets. The PFA was then focused on the ILD sections in the vicinity of the Cu pillar interconnect (as the pillar is the primary load transference link between the die and substrate). Specific fail modes were then identified using a combination of Scanning Optical Microscopy (SOM), Scanning Acoustic Microscopy (SAM), layer by layer de-processing and Focused Ion Beam (FIB) cross-sections. The paper summarizes the key findings, failure modes from the study — it was found that the assembly process could result in damage initiation in the ILD which results in functional failures during subsequent reliability testing. The scale of induced damage makes it nearly impossible to detect using either traditional eFA, PFA or a combination of the two. Additionally, key assembly and design parameters, to resolve the fails are also discussed.

Failure analysis (FA) is a basic and effective method to obtain the physical and failure information of electronic components and circuits. Most of these information can provide many useful evidences for prognostic and system health management (PHM) of electronic products. To obtain these information, many failure analysis techniques are used. This paper focuses on analyzing the relationship between FA techniques and PHM system. To test and verify the availability of the relationship between FA techniques and PHM system, a failure analysis case of an Intelligent Power Module (IPM) is used to study the relationship. This IPM contains six insulated gate bipolar transistors (IGBTs) and there are obvious burnout indications on most of them after failure. With the process of failure analysis, the key information, such as component's structure, sensitive parameters are identified. These results persuasively prove that FA techniques can provide much information to PHM system, including PoF and data-driven methods.