Words for the “Whys”

Failure analysis (FA) is a basic and effective method to obtain the physical and failure information of electronic components and circuits. Most of these information can provide many useful evidences for prognostic and system health management (PHM) of electronic products. To obtain these information, many failure analysis techniques are used. This paper focuses on analyzing the relationship between FA techniques and PHM system. To test and verify the availability of the relationship between FA techniques and PHM system, a failure analysis case of an Intelligent Power Module (IPM) is used to study the relationship. This IPM contains six insulated gate bipolar transistors (IGBTs) and there are obvious burnout indications on most of them after failure. With the process of failure analysis, the key information, such as component's structure, sensitive parameters are identified. These results persuasively prove that FA techniques can provide much information to PHM system, including PoF and data-driven methods.

Defect isolation and failure analysis is a key factor that drive development and manufacturing yield improvements in semiconductor packaging industry. From a manufacturing point of view, ensuring adequate package reliability is becoming more challenging due to increasing packaging complexity and a more pronounced impact from material physical property mismatch among packaging materials and components. The task of isolating defects and finding root cause is further complicated by ever shrinking feature sizes within the device and/or package, already approaching the nanometer range in contemporary semiconductor packages. Conventional failure analysis techniques such as physical cross sectioning or micro-cutting using focused ion beams(FIB) are sometimes no longer sufficient to find these defects. Both physical cross section and FIB are only capable of exposing the defect in two dimensions (x and y directions), which makes pinpointing the defect in depth, i.e., the z direction, extremely difficult when dealing defects with micron and submicron size. Additional complications are many times introduced during conventional sample preparation, which can introduce undesirable artifacts associated with the module and/or device depackaging. These artifacts may mask the true defects, or lead to misinterpretation of the true cause of failure. In this work, it has been determined that a three-dimensional failure analysis method is critical for finding some defects in silicon packages. For example, xenon difluoride (XeF2) has excellent selectivity to silicon and provides efficient material removal by chemical reaction, generating gaseous by-products that can be readily exhausted [1]. Furthermore, XeF2 has very little reaction with non-silicon materials, such as SiO2, and the metals and polymers commonly used in semiconductor devices and packages. This paper reports the application of XeF2 as an effective failure analysis technique to reveal defects in silicon packages. The mechanism of selective reaction between XeF2 and Si is discussed and key design features of the failure analysis tool are presented. The paper also highlights a few case studies which advantageously utilize XeF2 etching to expose defects. XeF2 was especially effective in detecting the source of electrical leakage in 3D packages having Through Silicon Via (TSV) structures. Due to its high etching selectivity to silicon, the leakage area in electrically failing samples was found to be due to damage of the TSV liner (passivation layer material) and further analysis reveals a three dimensional view of the TSV defect. With the addition of XeF2 etching, further characterization of defects by traditional methods such as FIB micro cutting also becomes more practical. The work suggests that a wider application of Si removal via XeF2 can be achieved by combining mechanical milling of bulk silicon followed by a final, low stress, silicon removal by XeF2 etching.

Detecting failure in electrical connectivity at the component packaging level is a major expenditure of the industry’s failure analysis (FA) resources. These package failures can result from material/manufacturing excursions, stress tests, and/or customer returns. However, many of the methods employed currently (such as X-ray or crosssectioning) can fall short in terms of throughput time, or success rate. Moreover, many FA techniques can be destructive and therefore leave the sample useless for subsequent tests. On the other hand, time domain reflectometry (TDR) can be used as a component packaging level FA tool which meets the needs of quickly, precisely, and non-destructively locating electrical connectivity problems in signal traces. Once the failure location has been pin pointed, other FA methods (X-ray, cross-section, etc.) can be used more easily to determine why the failure occurred. Since TDR testing involves no physical preparation, the sample will be completely intact for subsequent tests. TDR uses a low voltage, low current, and very short rise time voltage pulse to determine the impedance of a signal trace as a function of time. With a waveform of trace impedance versus time, not only can the presence of a failure be detected, but the distance along the trace to the anomaly can also be quickly determined. This paper presents TDR as a useful tool for package level failure analysis labs. The paper proposes one set of solutions for enabling effective TDR analysis (e.g., TDR test fixturing), and discusses some TDR methodologies for detecting and locating anomalies. The methodologies will be illustrated using three example cases that reflect some commonly used packaging technologies: Flip-Chip Organic Land Grid Array (FC-OLGA), Flip-Chip Pin Grid Array (FC-PGA), and Plastic Land Grid Array (PLGA).

Owing to the configuration of cavity up and stacked die packaging and the requirements of backside analysis, both packaging types require similar sample preparation steps. This article describes the failure analysis (FA) process to be applied with cavity up and stack die packages. The FA process flow includes testing to determine the nature of the failure, failure correlation to chip and/or internal circuitry, die preparation for repackaging, die repackaging in a cavity down configuration, automated test equipment (ATE) testing to verify the integrity of the pre-packaging failure mode, backside thinning, global fault isolation, backside reconstruction, and defect identification by front side deprocessing. ATE FA can often be performed using special analysis modes and the modification of the test software to put tester in a halt or a loop during fault isolation. When this is completed, global FA techniques can be used. The article also presents a case study on the successful repackaging efforts of cavity up packages.

Purpose Emergency shutdown (ESD) systems play a critical role in ensuring safety and availability of oil and gas production. The systems are operated in on-demand mode, and the detection and prediction of their failures is deemed challenging. The purpose of this paper is to develop a logical data-driven approach to enhance the understanding and detectability of ESD system failures. Design/methodology/approach The study was conducted in close collaboration with the Norwegian oil and gas industry. The study and analyses were supported by industrial data, failure data generated in a test facility in Norway and domain experts. Findings The paper demonstrated that there is a considerable potential to improve the decision process and to reduce the workload related to ESD systems by means of a logical data-driven approach. The results showed that the failure analysis process can be executed with more clarity and efficiency. Common cause failures could also be identified based on the suggested approach. The study further underlined the requirements regarding relevant data, new competence and technical supports in order to improve the current practice. Originality/value The paper leveraged the value of real-time data in identifying failures through mapping of the interrelationships between data, failure mechanisms and decisions. The failure analysis process was re-designed, and the understanding and decision making related to the system was improved as a result. The process developed for ESDs can further be adapted as a common practice for other low-demand systems.

Conventional focussed ion beam (FIB) based specific area transmission electron microscopy (TEM) sample preparation techniques usually requires complex grinding and gluing steps before final FIB thinning of the sample to electron transparency (<0.25 μm). A novel technique known as lift-out, plucking or pullout method that eliminates all the pre-FIB sample preparation has been developed for specific area TEM sample preparation by several authors. The advantages of the lift-out procedure include reduced sample preparation time and possibility of specific area TEM sample preparation of most components of integrated circuit with almost no geometric or dimensional limitations. In this paper, details of liftout method, developed during the present work, for site specific x-sectional and a new site specific planar sample preparation are described. Various methodologies are discussed to maximize the success rate by optimizing the factors that affect the technique. In failure analysis, the geometric and dimensional flexibility offered by the lift-out technique can be used to prepare specific area TEM sample of back thinned die, small particles and packaged parts. Such novel applications of lift-out technique in failure analysis are discussed with the examples of TEM results obtained from GaAs and Si based devices. Importantly, it was possible to obtain high resolution lattice images from the lift-out samples transferred on holey carbon supported 3mm copper grids.

Failure analysis on 14 nm FinFET devices with ESD CDM failure

Hard disk failure is a serious problem in term of product quality and credibility to customers. All hard disk drive companies need to be aware and address how to get rid of failure and prevent the repeat of the problem in their products. The quality of failure analysis process depends on the person who has most experience. It would not be so efficient if the company has no experienced person to perform the analysis. A knowledge management system can store the knowledge of experienced engineers. It can help new engineers to learn the craft. It would reduce a knowledge gap issues and bring up efficiency for failure solving process. This paper presents a design and implementation of knowledge management system for failure analysis in hard disk with case-based reasoning. The existing cases are stored and a new case can be compared to the existing one in order to retrieve the relevant existing knowledge to help the analysis. Once the new case is solved, it can be stored to aid the future cases. A prototype of the system has been implemented and the assessment of user satisfaction shows that it can improve the failure analysis process effectively.

Cell performance, or efficiency, η% is the most used, if not most important metric for evaluating different solar cell technologies. Efficiency in turn is determined directly by the product of open-circuit voltage, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">oc</sub> , short-circuit current density, J <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sc</sub> , and fill-factor, FF. From numerous studies involving the measurement of η% as a function of stress, it has been determined that η% can be most correlated with changes in FF. In order to better study changes in FF, and thus, to better understand what causes cells to degrade, we have developed a new and appropriate failure analysis technique which can be readily incorporated within the framework of existing accelerated lifetime testing (ALT). This non-destructive, two-terminal technique is relatively easy to perform on both polycrystalline thin film solar cells as well as finished series-connected thin film modules and is believed to be benign as a failure analysis tool. In this technique, capacitance data is collected using a bi-directional voltage scan in order to capture commonly observed hysteretic or “transient” effects in polycrystalline thin film cells and modules.

Failure analysis (FA) plays an important role in semiconductor industry as the process technology and new packaging are continuously improved. Fault localization is a key step to narrow down the area of failed part and isolate the defective areas, which is prior to destructive failure analysis. This paper will cover some advanced fault localization techniques and tools in package and die/device level failure analysis. Case studies for those techniques will provide a good understanding and illustrate the applications.

This paper describes a new technique, called the Light-Induced State Transition (LIST) method that uses an optical beam induced current (OBIC) system for failure analysis of CMOS LSIs. This technique allows one to locate a low signal line short-circuited to a GND bus (or a high signal line short-circuited to a V/sub DD/ bus) in stand-by condition which is not possible with conventional failure analysis techniques such as photo-emission analysis, liquid crystal technique, or the conventional OBIC method. The effectiveness of the LIST method was verified by an experiment on inverter chains that included quasi-failures intentionally patched by FIB deposition. The LIST method has also been used for actual CMOS logic failure analysis, and has proved to be useful for finding a failure location rapidly.

An object-oriented approach for constructing an IC failure analysis system environment named MultiICFA is described. The MultiICFA enables the failure analyst to manage IC analysis information, which consists of video, graphical plot, film, image, and text description, through a user interface. In this paper, the characteristics of failure analysis in an IC device are described and a process of failure analysis, which is currently used by an IC manufacturer, is given. The architecture of the MultiICFA is outlined, which focuses on modelling and management of data. An object-oriented approach to design is adopted in the implementation of the system

Xradia has developed a laboratory table-top transmission x-ray microscope, TXM 54-80, that uses 5.4 keV x-ray radiation to nondestructively image buried submicron structures in integrated circuits with at better than 80 nm 2D resolution. With an integrated tomographic imaging system, a series of x-ray projections through a full IC stack, which may include tens of micrometers of silicon substrate and several layers of Cu interconnects, can be collected and reconstructed to produce a 3D image of the IC structure at 100 nm resolution, thereby allowing the user to detect, localize, and characterize buried defects without having to conduct layer by layer deprocessing and inspection that are typical of conventional destructive failure analysis. In addition to being a powerful tool for both failure analysis and IC process development, the TXM may also facilitate or supplant investigations using scanning electron microscopy (SEM), transmission electron microscopy (TEM), and focused ion beam (FIB) tools, which generally require destructive sample preparation and a vacuum environment.

Guide for authors — Geo-Science Publications

Focused ion beam (FIB) is commonly used as a standard machining technique in failure analysis, quality control, reverse engineering, material research, and so on, for the samples having microstructures and nanostructures. FIB combined with time‐of‐flight secondary ion mass spectrometry (TOF‐SIMS), so‐called FIB‐TOF, has attracted attention as a method to determine the three‐dimensional (3D) chemical distributions of complex samples. In general, a highly focused Ga + ion beam is used for FIB, however, the FIB‐milled area is limited and it was difficult to expand the Ga‐FIB to hundreds of micron length scale for sample fabrication. In order to overcome the drawback, we proposed the Bi‐FIB approach for large scale sample cross‐sectioning. Although the possibility of Bi‐FIB has been reported, there were almost no performance examinations as well as practical applications. In this study, therefore, the authors summarize the comparison of milling rate and milling damage between Ga‐FIB and Bi‐FIB. As a result, it was found that Bi‐FIB can provide a higher milling rate with thinner milling damage. Finally, the Bi‐FIB approach was applied to the interfacial analysis of all‐solid‐state battery (ASSB) material. With this approach, the detailed chemical distributions at the interface were discovered, leading to the better understanding of battery behaviors.