Failure Analysis of Stacked-Chip Scale Package

A general defect modelling and simulation-assisted approach for fault isolation in failure analysis

As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically, especially for implantation related problems [1] [2]. Implantation related defects, or invisible defects, are the most challenging defect types for the application of fault isolation in all of the failure analysis jobs. The key challenge for these kinds of analyses is to make the defect visible. Sometimes, it is difficult or even impossible to visualize the defective point. Then, sufficient electrical evidence and theory analysis are important to bring the issue to resolution. For these kinds of analyses, a nanoprobing system is a necessary tool to conduct the detailed analysis. Combined with the device physics and electrical theory analysis, nanoprobing can bring out the perfect failure mechanism and problematic process step. There are two popular nanoprobing systems in our lab, one is SEM based and the other is AFM based. Both systems have their advantages and disadvantages in the electrical characterization and fault isolation field. In this paper, an implantation related issue was analyzed. Gross leakage was observed on the failed units as compared with good units. Global fault isolation, TIVA and EMMI failed to find the exclusive hotspot. With the GDS and process analysis, the nanoprobing was employed to the performance check on some of the suspected structures. Finally, the defective location was successfully isolated by nanoprobing. Combined with device physics and electrical analysis, the problematic process was successfully isolated.

Owing to the configuration of cavity up and stacked die packaging and the requirements of backside analysis, both packaging types require similar sample preparation steps. This article describes the failure analysis (FA) process to be applied with cavity up and stack die packages. The FA process flow includes testing to determine the nature of the failure, failure correlation to chip and/or internal circuitry, die preparation for repackaging, die repackaging in a cavity down configuration, automated test equipment (ATE) testing to verify the integrity of the pre-packaging failure mode, backside thinning, global fault isolation, backside reconstruction, and defect identification by front side deprocessing. ATE FA can often be performed using special analysis modes and the modification of the test software to put tester in a halt or a loop during fault isolation. When this is completed, global FA techniques can be used. The article also presents a case study on the successful repackaging efforts of cavity up packages.

Failure analysis (FA) could provide timely feedback to process optimization and solution paths for system failures; thus, it is critical for the development of advanced driver assistance systems (ADAS). In this chapter, failure analysis flows starting from systems or boards until components or packages and dice are introduced. Electrical fault isolation (FI) techniques designed to locate subtle defects inside complicated semiconductor devices are reviewed. Physical failure analysis approaches adopted to provide artifact free nanometer scale analysis are discussed. Material analysis methods assisting in thorough root cause investigation are presented. Non-destructive and high-resolution imaging tools with the potential of significantly shortening failure analysis through put time are demonstrated. Case studies are used to illustrate strategies and methodologies in ADAS failure analysis.

This paper analyzes the through-put time and output of fault isolation and failure analysis (FI/FA) flows on state-of-the-art microprocessors. An average reduction in through-put time of 40% was demonstrated with a shortened FI/FA flow while still maintaining a high success rate. The direct FA/nano-probing flow which was utilized by up to around 90% of the fail cases omitted the optical fault isolation step and instead expanded the use of plasma FIB, nano-probing and electrical isolation techniques (such as diagnosis tools). The end result is shorter through-put time and higher FI/FA volume which is important in order to achieve a faster production ramp. In the paper two cases studies are presented to demonstrate the new efficient FI/FA techniques.

Strength and failure analyses are critical to the safe and sustainable design of any structure. In the case of adhesively bonded joints, particular attention must be paid to the adhesive layer, which is comparably compliant and subject to high stresses. Determining the stresses in the adhesive layer is essential to identify critical areas in the joint and prevent the formation of cracks. In most applications, bonded joints have thin adhesive layers that can already be accounted for with highly simplified analytical models. However, for the consideration of thicker adhesive layers, advanced models are required that take the adhesive layer into account in more detail.Therefore, in this work, an analytical model with a higher‐order displacement approach is presented to account for more complex deformation behavior in the adhesive layer. The applied advanced displacement approach is particularly suitable for joints with thicker adhesive layers. In addition, the model enables the calculation of stresses and strains in bonded joints for a wide range of joint configurations and applications. A parameter study is carried out to evaluate the effect of different thicknesses of the adhesive layer and to show the advantages of the current model compared to other existing ones. For verification, all analytical results were compared with corresponding Finite Element Analyses.

Semiconductor trends as embodied in the International Technology Roadmap for Semiconductors (ITRS) provides a guide for the challenges facing the failure analysis community. The technical challenges fall primarily into two categories: failure site isolation and physical analysis. The failure site isolation challenges are driven primarily by the device complexity and reduced accessibility of circuit nets. Additional challenges arise due to the increase in device operating speed and pin count. The challenges in physical analysis are driven primarily by smaller device feature sizes and by the host of new materials being introduced. In addition to the technical challenges, infrastructure changes are also likely to occur. The likely industry paths for addressing these challenges are discussed. The International Sematech Product Analysis Forum (Joseph et al, 2000) has identified ten primary challenges for the future of the failure analysis in the semiconductor industry: localization and electrical characterization; deprocessing techniques for new materials; system-on-a-chip; imaging of small defects and structures; detection and characterization of nonvisual defects; verification and test; globally dispersed entities as virtual factory; fault isolation and simulation software; cost of failure analysis; complexity and volume of data. These challenges have been correlated to the Technology Working Group Difficult Challenge table in the ITRS.

Integrated capacitors use metal plates such as in Metal-Insulator-Metal (MIM) and Metal-Oxide-Metal (MOM) capacitors while Polysilicon and Silicon (Si) substrate for metal-oxide-semiconductor (MOS) capacitors. Three major challenges and solutions were discussed in this technical paper. First, the failure site localization of a subtle defect in the capacitor plates. To determine the specific location of the defect site, Electron Beam Induced Current (EBIC) analysis was performed while the part was biased using a nano-probe set-up under Scanning Electron Microscopy (SEM) environment. Second, Failure Mechanism contentions between Electrically Induced Physical Damage (EIPD) or Fabrication process defect particularly, for damage site that is not at the edge of the capacitor and without obvious manifestations of Fabrication process anomalies such as bulging, void, unetched material or shifts in the planarity of the die layers. To further understand the defect site, Scanning Transmission Electron Microscopy (STEM) coupled with Energy-Dispersive X-ray Spectroscopy (EDS) were utilized to obtain high magnification imaging and elemental area mapping. Third, misled conclusion to be an EIPD site manifested by burnt and reflowed metallization. The EIPD site was only a secondary effect of a capacitor dielectric breakdown. This has been uncovered after understanding the circuit connectivity, inspections of the capacitors connected to the EIPD site, fault isolation and further physical failure analysis were performed. As results of the Failure Analysis (FA), Customer and Analog Devices Incorporated (ADI) manufacturing hold lots were accurately dispositioned and related corrective actions were precisely identified and implemented.

Detecting failure in electrical connectivity at the component packaging level is a major expenditure of the industry’s failure analysis (FA) resources. These package failures can result from material/manufacturing excursions, stress tests, and/or customer returns. However, many of the methods employed currently (such as X-ray or crosssectioning) can fall short in terms of throughput time, or success rate. Moreover, many FA techniques can be destructive and therefore leave the sample useless for subsequent tests. On the other hand, time domain reflectometry (TDR) can be used as a component packaging level FA tool which meets the needs of quickly, precisely, and non-destructively locating electrical connectivity problems in signal traces. Once the failure location has been pin pointed, other FA methods (X-ray, cross-section, etc.) can be used more easily to determine why the failure occurred. Since TDR testing involves no physical preparation, the sample will be completely intact for subsequent tests. TDR uses a low voltage, low current, and very short rise time voltage pulse to determine the impedance of a signal trace as a function of time. With a waveform of trace impedance versus time, not only can the presence of a failure be detected, but the distance along the trace to the anomaly can also be quickly determined. This paper presents TDR as a useful tool for package level failure analysis labs. The paper proposes one set of solutions for enabling effective TDR analysis (e.g., TDR test fixturing), and discusses some TDR methodologies for detecting and locating anomalies. The methodologies will be illustrated using three example cases that reflect some commonly used packaging technologies: Flip-Chip Organic Land Grid Array (FC-OLGA), Flip-Chip Pin Grid Array (FC-PGA), and Plastic Land Grid Array (PLGA).

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Ceramic is widely used in high reliability microelectronic packaging as its excellent properties. Generally, failure analysis for ceramic flip-chip structure is more difficult than other traditional types considering its special structure. Interconnection open failures of a flip-chip device in reliability testing were studied, and a test scheme from NDE to DPA was developed. The possibility of internal failure of the substrate was eliminated through TDR test. The failure position was preliminarily determined by X-ray, SAM and optical microanalysis. And finally, the nickel layer was found to be the accurate failure position of the device which was realized through SEM&EDS. The failure analysis method can be used for reference for failure detection and analysis of other ceramic flip-chip packages.

The traditional fault isolation strategy based on the rollout algorithm will increase the algorithm time complexity and use too many test points. The optimization strategy of tests for fault isolation based on rollout algorithm can solve these problems, and make the final optimization result is still better than the normal rollout algorithm. This optimization strategy not only makes the rollout algorithm effective, maximizes the system fault isolation rate, but also reduces the time complexity of the algorithm, reduces the use of unnecessary tests, simplifies the complexity of the system, and improves the compatibility of the algorithm for complex systems. The principle of this optimization strategy is to perform fault isolation operations on all tests before using the rollout algorithm, and then use the rollout algorithm to sort the tests after selecting the necessary tests. Finally, the theoretical and case analysis results prove that the optimization strategy can use the least tests under the premise of ensuring the maximum fault isolation rate, reduce the time complexity of the rollout algorithm, and is suitable for optimizing the fault diagnosis of complex systems.

In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

In this paper we show an efficient workflow that combines Magnetic Field Imaging (MFI) and Dual Beam Plasma Focused Ion Beam (DB-PFIB) for fast and efficient Fault Isolation and root cause analysis in 2.5/3D devices. The work proves MFI is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) triple stacked devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a DB-PFIB system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects. With a DB-PFIB, the fault is exposed and analyzed without any sample prep artifacts seen in mechanical polishing or laser preparation techniques and done in a considerably shorter amount of time than that required when using a traditional Gallium Focused Ion Beam (FIB).

This article examines optical fault isolation (OFI) techniques based on heat diffusion for failure analysis of 3D devices, with a focus on thermoreflectance (TR) and laser-induced optical beam-induced resistance change (LI-OBIRCH). TR imaging enables wavelength-selectable probing with structure-dependent thermal coefficients, though performance depends on reducing light source noise. LI-OBIRCH demonstrates 3D analysis capability through a mathematical model and data processing algorithm validated by proof-of-concept experiments on thin 3D test samples. Both techniques show promise for analyzing 3D architectures, including backside power delivery networks and 3D NAND flash memories. Ongoing development addresses physics-related and algorithmic challenges to advance failure analysis capabilities for next-generation semiconductor devices.