Chapter 5 - Applications

In the surface mount technology, Ball Grid Array (BGA) has been used in a production of PC boards, because of their excellent characters such as high density of the lead pin pitch, better lead rigidity and self-alignment during re-flow processing. This paper deals with the development of image analysis for the detection of defects at BGA solder joints in PC boards by using X-ray images. In the conventional IC boards, it is possible to detect defects of solder joints by visual inspection, because the lead of IC package is set on its outside. However, we can't detect visually defects at BGA solder joints, because they are hidden under the IC package. In a production line, the inspection of BGA in PC boards depends on the function test of electric circuits in the final process. To improve a cost performance and the reliability of PC boards, an inspection of BGA is required in the surface mount process. Types of defects at BGA solder joints are solder bridge, missing connection, solder voids, open connection and miss-registration of parts. As we can find mostly solder bridge in these defects, we pick up this to detect solder bridge in a production line. The problems of image analysis for the detection of defects at BGA solder joints are the detection accuracy and image processing time according to a line speed of production. To get design data for the development of the inspection system, which can be used easily in the surface mount process, it is important to develop image analysis techniques based on X-ray image data. At the first step of our study, we attempt to detect the characteristic of the solder bridges based on an image analysis.

5 - Applications

Surface mount technology (SMT) is being increasingly used in printed circuit board (PCB) assembly. The reduced lead pitch of surface mount components coupled with their increased lead count and packing densities have made it imperative that automated placement methods be used. However, the SMT placement process is often a bottleneck in surface mount manufacturing. A reduction in placement time in SMT will enhance throughput and productivity. This paper describes the design and development of a prototype expert system based approach which identifies ‘near’ optimal placement sequences for surface mount PCBs in (almost) realtime. The software structure used integrates a knowledge based system with an optimisation module. PROLOG is the language used in this research. The system was rigorously validated and tested. Ideas for further research are also presented.

The surface mounting of electronic component is the major manufacturing technology for the electronic products in the last decade. The surface mounting technology (SMT) is an assembly process that assembles the surface mountable component (SMC) and the printed circuit board (PCB) together. The SMT mounter is an automatic assembly machine that processes the SMT assemblies in terms of the optical positioning and robotic handling. The SMT assembly consists of calibrating printed circuit board (PCB); vacuuming components form feeder stations; compensating the orientation of the vacuumed surface mountable component (SMC); and finally placing SMC chips on the PCB. In order to increase the throughput, the synchronous batch vacuuming of SMC components is designed. In addition, different types of component feeding and mixing in each batch increase the difficulties of finding the best component mounting sequence. In this paper, the optimal component placement scheduler is desired to perform higher assembly performance and to reduce the cycle time. The proposed optimal component placement scheduler is developed based on the rule based heuristic search approach. In addition, to evaluate the cycle time of each heuristic search, the route oriented Petri nets (ROPN) based SMT assembly models are constructed. The optimal component placement scheduler can be further determined in terms of evaluating the ROPN SMT assembly models. Finally, the practical test PCB board data is discussed in this paper.

A point-of-load power supply is designed for use in a distributed power system. In order to be commercially viable this supply requires low-cost components and packaging, while maintaining a small footprint and a half-inch height for interboard spacing requirements. The unique combination of direct-bond copper, surface mount, and advanced magnetic technologies permits an estimated maximum hybrid power density of 40 W/in/sup 3/ while using low-cost, readily available commercial components. Packaging details of a 100 W prototype operating at 1 MHz with 34 W/in/sup 3/ hybrid power density are described, including packaging constraints caused by the electrical requirements of the resonant topology utilized. In addition, thermal considerations which must be met in order to reach the maximum hybrid power density are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The long-term reliability of surface mount (SM) solder interconnections remains an important issue in many critical electronics packaging applications. Compliant leads are typically post-attached to leadless ceramic chip carriers (LCCCs) and multichip modules (MCMs) to enhance the SM attachment reliability margin on organic substrates. The various lead-forms are commercially available in edge-clip, soldered, and thermocompression (TC) bonded designs for component attachment. Compliance evaluation was performed for a representative corner-most solder connection on a LCCC. The effective stiffness of the solder joint and commercial post-attached lead designs were compared in order to demonstrate the SM interconnection reliability advantage provided by certain edge-clip and TC-bonded lead-forms. Commercial high-compliance edge-clip, soldered, and TC-bonded lead designs have diagonal-direction stiffness between nominally 10-40 lb/in, prior to circuit-board attachment. The compliant leads accommodate a large part of the component-substrate thermal expansion mismatch, significantly reducing the cyclic loads transmitted to the comparatively noncompliant solder connections. The diagonal stiffness results for the corner-most solder joint are specific for the particular contour and dimensions of the FE structural model. However, the current study provides fundamental understanding of the compliance advantage of post-attached leads compared to leadless SM interconnections. >

: As electronic products become much smaller, a limiting factor in the reduction of product size has been the size of electronic components which make up the product. The leads of the current electronic components are inserted onto a printed circuit board through holes. Due to the use of wire leads, it becomes more difficult to decrease the size of the components. A new method was created to mount components directly to the surface of the printed circuit board. This new technique is surface mount technology. A concern over the use of this is experienced by the military. Since the leads are not inserted through the board and crimped before soldering as conventional components are mounted, there is some regard as to whether the components can be mounted securely to the board. Due to the high forces that many munitions experience when dispensed, it is imperative that the electronic components be soldered to the circuits boards so they will not slip out of place or fall from the board. The military also requires many munitions to lie dormant in storage warehouses for up to 20 years. When the munition is needed, it must perform reliably. Little work has been done to study the effects of this long-term storage on these surface mount devices particularly the ability of different soldering techniques used to attach surface mount components to printed circuit boards to withstand damaging effects of long-term storage.... Surface mount technology, Solderability, Wave soldering, Reflow soldering, Conductive adhesive curing, Long-term storage, Accelerated age testing.

The New England Lead-free Electronics Consortium is a collaborative effort of New England companies spanning the electronics supply chain, created by the University of Massachusetts Lowell in 1999 and sponsored by the Toxics Use Reduction Institute and the U.S. EPA. The consortium has completed and published the results of three phases of manufacturing and testing of lead-free Printed Wiring Boards (PWBs) with the goal of achieving zero-defect leadfree soldering processes with comparable or superior reliability to that of leaded solder processes. In this fourth phase of testing, which began in 2007, several simulated conditions of assembly and rework processes were evaluated in a matrix of multiple levels of components, PWB lead free surface finishes and solders, and compared to a baseline of leaded equivalent materials and processes. Both Through Hole (THT) and Surface Mount (SMT) Technologies were evaluated. The assembly portion of the testing and rework is completed and the long term reliability and vibration is ongoing. All quality and reliability testing was performed with industry standard methodologies, using specially trained production inspectors for the quality evaluation, and extreme thermal cycling for reliability testing. Our results indicate that with proper selection of currently available (2008) materials and finishes and careful control of the assembly processes, successful lead free assembly and rework can be achieved. Comparison of different strategies for rework, and recommendations for least copper dissolution for THT technology processes are discussed in the published book by the paper authors. Reliability testing to date showed interesting inflection points for leaded versus lead free reliability that has to be resolved by additional thermal cycling, to be published when completed in 2009, together with vibration testing.

Life testing/qualification of reflowed (1 st reflow) and reworked (1 st reflow, 1 st removal, and then 1 st rework) advanced ceramic column grid array (CCGA) surface mount interconnect electronic packaging technologies for future flight projects has been studied to enhance the mission assurance of JPL-NASA projects. The reliability of reworked/reflowed surface mount technology (SMT) packages is very important for short-duration and long-duration deep space harsh extreme thermal environmental missions. The life testing of CCGA electronic packages under extreme thermal environments (for example: -185°C to +125°C) has been performed with reference to various JPL/NASA project requirements which encompass the temperature range studied. The test boards of reflowed and reworked CCGA packages (717 Xilinx package, 624, 1152, and 1272 column Actel Packages) were selected for the study to survive three times the total number of expected temperature cycles resulting from all environmental and operational exposures occurring over the life of the flight hardware including all relevant manufacturing, ground operations, and mission phases or cycles to failure to assess the life of the hardware. Qualification/life testing was performed by subjecting test boards to the environmental harsh temperature extremes and assessing any structural failures, mechanical failures or degradation in electrical performance solder-joint failures due to either overstress or thermal cycle fatigue. The large, high density, high input/output (I/O) electronic interconnect SMT packages such as CCGA have increased usage in avionics hardware of NASA projects during the last two decades. The test boards built with CCGA packages are expensive and often require a rework to replace a reflowed, reprogrammed, failed, redesigned, etc., CCGA packages. Theoretically speaking, a good rework process should have similar temperature-time profile as that used for the original manufacturing process of solder reflow. A multiple rework processes may be implemented with CCGA packaging technology to understand the effect of number of reworks on the reliability of this technology for harsh thermal environments. In general, reliability of the assembled electronic packages reduces as a function of number of reworks and the extent is not known yet. A CCGA rework process has been tried and implemented to design a daisy-chain test board consists of 624 and 717 packages. Reworked CCGA interconnect electronic packages of printed wiring polyimide boards have been assembled and inspected using non-destructive x-ray imaging and optical microscope techniques. The assembled boards after 1 st rework and 1 st reflow were subjected to extreme temperature thermal atmospheric cycling to assess their reliability for future deep space JPL/NASA for moderate to harsh thermal mission environments. The resistance of daisy-chained interconnect sections were monitored continuously during thermal cycling to determine intermittent failures. This paper provides the experimental reliability test results to failure of assemblies for the first time of reflowed and reworked CCGA packages under extreme harsh thermal environments.

Conductive adhesives have been widely used in die mounting and component terminal bonding in certain types of hybrid circuits for a number of years. ECA (Electrically conductive adhesive) is an alternative to lead-free solder for certain specific applications in electronic products. Low processing temperature, fine pitch, flexible process steps, and no flux residues are some of the major advantages when using ECA for electrical interconnection between SMDs (surface mount devices) and the printed circuit board (PCB) in SMT (surface mount technology). ECA use a polymer matrix (such as epoxy) filled with conducting fillers (such as copper or silver); silver is used commonly due to its high conductivity and wide availability. The particle size (typically less than 40 microns) is controlled by the screen mesh used to sort the fillers. The study results indicated that it is feasible to incorporate ICA into current SMT production lines and can provide an alternative for solder replacement for specific product applications.

This paper reports on the planning, introduction, and implementation of surface mount technology (SMT) for printed circuit board assembly at Convergent Technologies. It is written from the production personnel's view‐point. The report starts with a brief history of the company, describes its dynamic environment, outlines the factors that led to the decision to implement SMT and provides the time‐frame for said implementation. With this background the paper then deals at length with design and manufacturing issues and questions that arose during this undertaking. The report concludes with a summary that outlines the benefits and concerns of SMT and highlights the future trends for this technology.

Electronic components continue to shrink as electronic printed circuit boards become denser. Smaller discrete passive devices such as surface mount capacitors and resistors are increasing in use and approaching sizes that require magnification to recognize. Unfortunately, during the Surface Mount Technology (SMT) assembly process these smaller devices are the primary source of defects during soldering. One of the leading defects during SMT is “Tombstoning,” a condition where a capacitor or resistor only solders on one end due to vertical rotation of the component creating an open circuit. Rework is costly and potentially induces additional factors that can decrease overall reliability because rework requires heating the defect location multiple times with a soldering iron; once to remove and once to replace for each pad. This defect can be drastically reduced by using the correct printed circuit board design parameters when laying out the board pad geometries. Printed Circuit Board pad size and geometry play a significant role in reducing and eliminating “tombstoning.” This paper presents the results from a comprehensive Designed Experiment illustrating the effects of different pad designs and their effect on the amount of defects. The results show that smaller pad geometries are a major factor in the reduction of “tombstoning.” This combined with the elimination of solder mask between the pads yield significant reduction in SMT soldering defects. This paper will delineate the major factors involved and how a comprehensive Design of Experiment (DOE) was planned and performed to drastically reduce this type of defect.

A study was performed to develop a different experimental methodology to assess wettabilities of solders on various printed wiring board (PWB) finishes, based on a modified spreading test in which solder pastes were heated following temperature reflow profiles representative of those used in surface mount technology (SMT) instead of using a fixed rate temperature ramp. Three solder alloys (Sn63‐Pb37, Sn96.5‐Ag3.5, and CASTINTM: Sn96.2‐Ag2.5‐Cu0.8‐Sb0.5), two fluxes (rosin, mildly activated, RMA, and no‐clean, NC), and seven PWB finishes (Pd, Au/Ni, Ni, Ag, Sn, and organic solderability preservatives: OSP), and bare copper were involved in the study. Better wettabilities were observed in the current study than the results reported in the literature for conventional tests on the same combination of solder alloy, flux, and substrate. The different results in measurement of wettabilities obtained in the current study were attributed to the more adequate heating process allowing flux activation, which reduced reoxidation of solder powders and substrates during the reflow process and thus improved wettabilities of solders. Compared to the results obtained from the popular wetting balance test, the current study demonstrated a more realistic simulation of, and approach to, assessing the wettability of solder for SMT.

Surface mount manufacturing technology quality and automation

The wide range of applications for medical electronics drives unique requirements that can differ significantly from commercial &amp; military electronics. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. In the present report, key enablers for achieving reduction in size, weight, and power (SWaP) in electronic packaging for a variety of medical applications are discussed. Advanced microelectronics packaging solutions with embedded passives are enabling SWaP reductions. Implementation of these solutions has realized up to 27X reduction in physical size for existing PWB assemblies, with significant reductions in weight. Shorter interconnects can also reduce or eliminate the need for termination resistors for some net topologies. Successful miniaturized products integrate the following design techniques and technologies: component footprint reduction, thin high density interconnects substrate technologies, I/O miniaturization and IC assembly capabilities. This paper presents fabrication and electrical characterization of embedded actives and passives on organic multilayered substrates. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on embedded chips, resistors, and capacitors. Embedded passive technology further enhances miniaturization by enabling components to be moved from the surface of the substrate to its internal layers. The use of thin film resistor material allows creating individual miniaturized buried resistors. These resistors provide additional length and width reduction with negligible increases to the overall substrate and module (SiP) height. Resistor values can vary from 5 ohm to 50 Kohm with tolerances from 5 to 20% and areas as small as 0.2 mm2. The embedded resistors can be laser trimmed to a tolerance of &amp;lt;5% for applications that require tighter tolerance. The electrical properties of embedded capacitors fabricated from polymer-ceramic nanocomposites showed a stable capacitance and low loss over a wide frequency and temperature range. A few test vehicles were assembled to do system level analysis. Manufacturing methods and materials for producing advanced organic substrates and flex along with ultra fine pitch assemblies are discussed. A case study detailing the fabrication of a flexible substrate for use in an intravascular ultrasound (IVUS) catheter demonstrates how the challenges of miniaturization are met. These challenges include use of ultra-thin polymer films, extreme fine-feature circuitization, and assembly processes to accommodate die having reduced die pad pitch. In addition, new technologies for embedding a variety of active chips are being developed. A variety of active chips, including a chip having dimensions of one millimeter square, have been embedded and electrically connected to develop high performance packages.