Characterization of asymmetries in 3D NAND memory devices

DRAM cell scaling down to the 14 nm design rule (D/R) has already been productized by major DRAM players such as Samsung, Micron, and SK Hynix. They’re developing n+1 (12~13 nm) and n+2 (11 nm or beyond) so-called D1b (D1β), D1c (D1γ), and D1d (D1δ) or even D0a generation now, which means DRAM cell D/R might be able to further scale down to single digit nm with EUVL adoption for DRAM cell/core patterning. The cell design scaling down is getting slower due to many scaling issues including patterning, leakage, and sensing margin. Major DRAM players have applied EUVL masks (such as SS_BLP/H_SC2) on DRAM and will expand it for the next generation. Current 6F2 cell architecture with 1T+1C will be moving over to 4F2 or 3D DRAM in an 8~9 nm D/R DRAM generation due to scaling limitations, which will be D0b or D0c. Although they change to 3D DRAM with a little relaxed CDs, EUVL will be a must for the performance and yield improvement (defects) in DRAM core areas such as very dense WLD and SA patterns just near the cell array. HKMG DRAM process has been adopted on Graphic DRAM and advanced DDR5 DRAM products by Samsung and Micron, although etching and high-k engineering are different for each. Major NAND manufacturers are still in the race to increase the number of vertical 3D NAND gates, they all have already introduced their own 176L/232L/238L 3D NAND devices. Samsung V-NAND, KIOXIA/WDC BiCS, Intel FG CuA, Micron CTF CuA, SK Hynix 4D PUC, and YMTC Xtacking 3D NAND products are the mainstream for SSD and mobile storage applications. Many innovative processes and designs have been adopted, however, lots of challenges are still there to overcome. Although lithography burdens were reduced by changing 2D to 3D, instead, UHAR etching/cleaning/filling-related developments are ongoing. Micron already exited XPoint memory, and Intel is winding it down as well. For SCM applications, fast NAND and some Emerging Memory (EM) devices such as Z-NAND, XL-FLASH, and STT-MRAM will cover the market needs in the future. Due to the difficulties of the EM materials etching, they’re currently limited to embedded and low-density applications only. We’ll discuss current and future challenges on DRAM, 3D NAND, and Emerging memory including process, design, and materials.

A machine learning (ML) method was used to optimize the trap distribution of the charge trap nitride (CTN) to simultaneously improve its performance/reliability (P/R) characteristics, which are tradeoffs in 3-D NAND flash memories. Using an artificial neural network (ANN), we modeled the relationship between trap distributions and P/R characteristics. The ANN was trained using a large experimentally calibrated technology computer-aided design (TCAD) simulation dataset. The gradient descent method was adapted to optimize the trap distribution, achieving the best P/R characteristics based on the well trained ANN. Eventually, we found the best trap profile distributed in both space and energy. In particular, the energetic trap distribution had a larger impact on the P/R characteristics than that of the spatial trap distribution. Furthermore, in terms of the P/R characteristics, it was generally preferable to increase all inputs of the energetic trap distribution. However, the acceptor-like trap energy level (ETA) and its standard deviation (sigma EA) caused a tradeoff between P/R characteristics; therefore, ML was used to determine their optimal points. The proposed ML method allows the optimization of trap distribution to obtain the best P/R characteristics rapidly and quantitatively. Our findings could be used as a guideline for determining the physical properties of CTN in 3-D NAND flash cells.

With an explosive growth of data generated by various applications, one of the most important topics of the current era is to increase the storage capacity. The evolution from 2D planar NAND to 3D NAND enables the development of high-density storage by increasing the number of stacked word-lines (WLs) in a smaller footprint. The industry has moved beyond 96-stacked-WL and achieved a 128-stacked 3D NAND. A 128-stacked 3b/cell 3D NAND with a density of 7.8Gb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was reported recently, based on a peripheral circuit under cell array (PUC) structure [1]. Nevertheless, due to the constant demand for increased density, 3D NAND faces the following challenges [2,3]: (1) a reduced PUC area due to an increasing WL stack, (2) increased load due to a higher number of stacks and a reduced spacing between WLs, (3) rising WL-channel capacitance due to an increasing number of strings, and (4) variation in the RC delay between WLs due to the non-uniformity of plug critical dimension (CD). Not only do these problems limit the density improvement of 3D NAND, but they also increase the WL rise time, which degrades read and write performance. This paper proposes the following techniques to overcome these challenges: (1) a 12-stage page buffer (PB) with one-to-one (1:1) PBUS(PB to cache connection bus), (2) a variable stage and frequency charge pump with a boosted local pump, (3) center X-decoder (XDEC) and half-plane activation, (4) an unselected string boosting scheme, and (5) adaptive WL overdrive (OVD). By applying these techniques, we achieved a density of 10.8Gb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 176stacked 3D NAND using 3b/cell.

ABSTRACTIn the presented study, the Sentinel-2 vegetation indices (VIs) were evaluated in context of estimating defoliation of Scots pine stands in western Poland. Regression and classification models were built based on reference data from 50 field plots and Sentinel-2 satellite images from three acquisition dates. Three machine-learning (ML) methods were tested: k-nearest neighbors (kNN), random forest (RF), and support vector machines (SVM). Regression models predicted stands defoliation with moderate accuracy. R2 values for regression models amounted to 0.53, 0.57, 0.57 for kNN, RF and SVM, accordingly. Analogically, the following values of normalized root mean squared error were obtained: 12.2%, 11.9% and 11.6%. Overall accuracies for two-class classification models were 78%, 75%, 78% for kNN, RF and SVM methods. The Green Normalized Difference Vegetation Index and MERIS Terrestrial Chlorophyll Index VIs were found to be most robust defoliation predictors regardless of the ML method. We conclude that Sentinel-2 satellite images provide useful information about forest defoliation and may contribute to forest monitoring systems.

Modeling and simulation softwareSection:ChooseTop of pageModeling and simulation s... <<Magnetocaloric effect mea...Semiconductor processing ...Computing and modeling so...Optical engineering softw...Semiconductor measurement...Automated wafer-level dev...Integrated circuit patter...Fluorescence imaging anal...Optical imaging and spect...Solder paste technologyAtomic layer deposition s...Comsol has released version 5.1 of its Multiphysics software, which allows users to create models, build simulation apps, and share the apps via the Comsol server mode. Upgrades include full integration between the model builder and the application builder. Users can easily switch between them and update the model and the app simultaneously. The model builder’s functions and features can be used in the application builder with no need to interface between the software packages. Both models and apps can be saved in the unified .mph file format. Version 5.1 simplifies code generation and provides many template codes for users who want to implement highly customized commands and operations. Additions have also been made to add-on products that expand the simulation platform for electrical, mechanical, fluid flow, and chemical applications. Comsol Inc, 1 New England Executive Park, Burlington, MA 01803, http://www.comsol.comMagnetocaloric effect measurement softwareSection:ChooseTop of pageModeling and simulation s...Magnetocaloric effect mea... <<Semiconductor processing ...Computing and modeling so...Optical engineering softw...Semiconductor measurement...Automated wafer-level dev...Integrated circuit patter...Fluorescence imaging anal...Optical imaging and spect...Solder paste technologyAtomic layer deposition s...A software analysis program from Lake Shore Cryotronics allows users in the magnetic research field to characterize and determine the nature of magnetic phase transitions in magnetocaloric effect (MCE) candidate materials. It is offered in a free beta trial version for users of Lake Shore’s 7400 or 7300 series vibrating sample magnetometers (VSMs). According to the company, the software simplifies the process of calculating MCEs and makes it easier to prepare the measuring protocol. The program imports measured isothermal M(H) and isofield M(T) magnetization curves recorded using Lake Shore VSM system data acquisition software. It uses those data to calculate the materials’ refrigerant capacity and their magnetic entropy change from peak value and full width at half maximum. Lake Shore Cryotronics Inc, 575 McCorkle Boulevard, Westerville, OH 43082, http://www.lakeshore.comSemiconductor processing failure analysisSection:ChooseTop of pageModeling and simulation s...Magnetocaloric effect mea...Semiconductor processing ... <<Computing and modeling so...Optical engineering softw...Semiconductor measurement...Automated wafer-level dev...Integrated circuit patter...Fluorescence imaging anal...Optical imaging and spect...Solder paste technologyAtomic layer deposition s...Park Systems has released the NX-Hivac atomic force microscope system for research and industrial failure analysis in highly doped semiconductor processing. It uses high-vacuum scanning spreading resistance microscopy to enable higher sensitivity and resolution than can be achieved in ambient conditions. The applied force between tip and sample under ambient or dry nitrogen conditions is four times higher than in a vacuum; the lower force under vacuum reduces the strain in thin films of target samples, which results in higher spatial resolution and longer tip life. The NX-Hivac can load up to five samples and measure a seven-decade dynamic range of dopant concentration. It has a closed-loop XY scanner for accurate zoom-in imaging and a low noise ratio of 0.30 Å. Motorized laser alignment and high-resolution axis optics enhance ease of use. Park Systems Inc, 3040 Olcott Street, Santa Clara, CA 95054, http://www.parkafm.comComputing and modeling softwareSection:ChooseTop of pageModeling and simulation s...Magnetocaloric effect mea...Semiconductor processing ...Computing and modeling so... <<Optical engineering softw...Semiconductor measurement...Automated wafer-level dev...Integrated circuit patter...Fluorescence imaging anal...Optical imaging and spect...Solder paste technologyAtomic layer deposition s...MathWorks has released version 2015a of its Matlab mathematical computing software and Simulink graphical environment for simulation and model-based design. Enhancements include new graphical controls and displays and antenna-to-bits simulation and testing of wireless communications and radar systems. It also has four new products: an antenna toolbox for designing, analyzing, and visualizing antenna elements and arrays; a robotics system toolbox for designing and testing algorithms for robotics applications; a Simulink test for creating test harnesses, authoring complex test sequences, and managing simulation-based tests; and a vision HDL toolbox with pixel-streaming algorithms for designing and implementing vision systems on field-programmable gate arrays and application-specific integrated circuits for image processing, video, and computer vision systems. The MathWorks Inc, 3 Apple Hill Drive, Natick, MA 01760-2098, http://www.mathworks.comOptical engineering softwareSection:ChooseTop of pageModeling and simulation s...Magnetocaloric effect mea...Semiconductor processing ...Computing and modeling so...Optical engineering softw... <<Semiconductor measurement...Automated wafer-level dev...Integrated circuit patter...Fluorescence imaging anal...Optical imaging and spect...Solder paste technologyAtomic layer deposition s...Photon Engineering has introduced version 14.40 of its optical engineering software, FRED. Used in product development, it merges optical elements with mechanical components to build integrated models. Among its improvements is increased flexibility in the feature that allows objects to be isolated in 3D view, since property-based isolation is now allowed. A new multiple selection method lets users simultaneously assign multiple properties such as coatings, ray-trace controls, and materials to different nodes in an object tree. Keywords, a new property in FRED, can facilitate complex model construction and configuration by acting as pass-throughs for objects assigned to them. A complete list of new FRED 14.40 features can be found in the developer release notes, accessible from the Help menu after installation. Photon Engineering LLC, 310 South Williams Boulevard, Suite 222, Tucson, AZ 85711, http://photonengr.comSemiconductor measurement toolSection:ChooseTop of pageModeling and simulation s...Magnetocaloric effect mea...Semiconductor processing ...Computing and modeling so...Optical engineering softw...Semiconductor measurement... <<Automated wafer-level dev...Integrated circuit patter...Fluorescence imaging anal...Optical imaging and spect...Solder paste technologyAtomic layer deposition s...Craic Technologies has developed its 20/30 XL microspectrophotometer to nondestructively analyze microscopic samples or microscopic areas on large devices, such as small-spot film thickness on 300-mm wafers. The instrument can acquire data by absorbance, reflectance, or luminescence spectroscopy. It can be used for UV-visible or near-IR microscopy and for high-resolution digital imaging of semiconductor and other types of samples. Users can add the company’s Apollo Raman spectroscopy modules to acquire Raman microspectra. Featuring calibrated variable apertures and manual and automated operation, the flexible instrument is designed to attach to large frames that can accommodate large-scale samples. Applications include mapping thin-film thickness of large devices, locating and identifying contaminants, and measuring strain in silicon. Craic Technologies Inc, 948 North Amelia Avenue, San Dimas, CA 91773, http://www.microspectra.comAutomated wafer-level device characterizationSection:ChooseTop of pageModeling and simulation s...Magnetocaloric effect mea...Semiconductor processing ...Computing and modeling so...Optical engineering softw...Semiconductor measurement...Automated wafer-level dev... <<Integrated circuit patter...Fluorescence imaging anal...Optical imaging and spect...Solder paste technologyAtomic layer deposition s...Keysight Technologies has unveiled WaferPro Express 2015, a software platform for high-volume measurement of wafer-level devices and circuit components for R&D applications such as device modeling, process monitoring, and component characterization. By controlling all components—instruments and wafer probers alike—WaferPro Express reduces setup complexity and provides a unified platform for efficient automated measurement and data management. It is integrated with Cascade Microtech’s Velox 2.0 probe station control software, a combination which allows for complete wafer-map synchronization. That enables easy, error-free information exchange between the software, including wafer alignment, sites, and die information. To maximize efficiency during RF measurement, WaferPro Express periodically monitors the stability of the RF calibration. Keysight Technologies Inc, 1400 Fountaingrove Parkway, Santa Rosa, CA 95403-1738, http://www.keysight.comIntegrated circuit patterning metrologySection:ChooseTop of pageModeling and simulation s...Magnetocaloric effect mea...Semiconductor processing ...Computing and modeling so...Optical engineering softw...Semiconductor measurement...Automated wafer-level dev...Integrated circuit patter... <<Fluorescence imaging anal...Optical imaging and spect...Solder paste technologyAtomic layer deposition s...The Archer 500LCM and SpectraFilm LD10, two advanced metrology systems from KLA-Tencor Corp, support the development and production of integrated circuit devices that are 16 nm and smaller. They are part of the company’s 5D patterning control solution that characterizes and monitors fab-wide processes. The Archer 500LCM system provides accurate overlay error feedback through all stages of the yield ramp, so chipmakers can resolve overlay issues associated with novel patterning techniques such as multipatterning and spacer pitch splitting. Through reliable, precise measurement of film thickness and stress, the SpectraFilm LD10 enables qualification and monitoring of the films and film stacks used in fabrication of FinFETs, 3D NAND, and other devices. KLA-Tencor Corporation, 1 Technology Drive, Milpitas, CA 95035, http://www.kla-tencor.comFluorescence imaging analysis softwareSection:ChooseTop of pageModeling and simulation s...Magnetocaloric effect mea...Semiconductor processing ...Computing and modeling so...Optical engineering softw...Semiconductor measurement...Automated wafer-level dev...Integrated circuit patter...Fluorescence imaging anal... <<Optical imaging and spect...Solder paste technologyAtomic layer deposition s...PicoQuant has released version 2.0 of its SymPhoTime 64 fluorescence-lifetime imaging microscopy (FLIM) and fluorescence correlation spectroscopy (FCS) software package. It provides new features for time-resolved data acquisition and analysis and for superresolution. They include global analysis of FCS and time-correlated single-photon counting (TCSPC) curve fitting, which improve cell measurements, and stimulated emission depletion data acquisition and analysis procedures, such as gated STED. An extended TCSPC binning functionality permits faster analysis and binary export of FLIM images. A newly developed fast pattern-matching approach allows two species to be separated by lifetime and absorption and emission spectra, thereby refining FLIM image analysis. PicoQuant, Rudower Chaussee 29, 12489 Berlin, Germany, http://www.picoquant.comOptical imaging and spectroscopy softwareSection:ChooseTop of pageModeling and simulation s...Magnetocaloric effect mea...Semiconductor processing ...Computing and modeling so...Optical engineering softw...Semiconductor measurement...Automated wafer-level dev...Integrated circuit patter...Fluorescence imaging anal...Optical imaging and spect... <<Solder paste technologyAtomic layer deposition s...Advancements in LightField version 5.0, an upgrade of Princeton Instruments’ scientific imaging and spectroscopy software, include a math engine for analyzing 64-bit data in real time, an interactive virtual optical bench for managing multiple experiment setups, and automatic export of data in various formats. LightField supports the latest Princeton Instruments hardware, including IntelliCal spectral-calibration light sources. When paired with LightField’s automated point- by-point wavelength and intensity calibration, IntelliCal improves wavelength accuracy and NIST-traceable, instrument-independent intensity data by a factor of 10. For time-resolved imaging and spectroscopy applications, LightField provides users with an intuitive oscilloscope-like timing interface to PI-MAX4 ICCD cameras for easy synchronization and gating controls. Princeton Instruments, 3660 Quakerbridge Road, Trenton, NJ 08619, http://www.princetoninstruments.comSolder paste technologySection:ChooseTop of pageModeling and simulation s...Magnetocaloric effect mea...Semiconductor processing ...Computing and modeling so...Optical engineering softw...Semiconductor measurement...Automated wafer-level dev...Integrated circuit patter...Fluorescence imaging anal...Optical imaging and spect...Solder paste technology <<Atomic layer deposition s...Indium Corporation offers its BiAgX solder paste as a drop-in replacement for the high-lead solders used in many high-reliability die-attach and electronics assembly applications. Made with the company’s high-melting solder paste technology, it can survive both high-temperature environments in excess of 175 °C with little degradation of the mechanical structure or other properties and J-STD-020 moisture sensitivity level reflow profiles up to 260 °C in the final solder joint. It does not contain lead, antimony, or specialty materials such as nanosilver or sintering aids. BiAgX reflows, solders, wets, and solidifies like any other solder paste. Available in both dispense and printing forms, it is suitable for small, low-voltage quad-flat no-lead packages used in portable electronics, automotive electronics, and industrial applications. Indium Corporation, 34 Robinson Road, Clinton, NY 13323, http://www.indium.comAtomic layer deposition systemSection:ChooseTop of pageModeling and simulation s...Magnetocaloric effect mea...Semiconductor processing ...Computing and modeling so...Optical engineering softw...Semiconductor measurement...Automated wafer-level dev...Integrated circuit patter...Fluorescence imaging anal...Optical imaging and spect...Solder paste technologyAtomic layer deposition s... <<The Savannah G2 atomic layer deposition (ALD) system from Ultratech Cambridge NanoTech incorporates advanced field-upgradable options that help researchers expand and characterize their portfolio of ALD films. One option is a low-vapor precursor delivery system that enables the growth of novel materials, including single- and multicomponent films from perovskite, yttrium, lithium, and the rare-earth families. Others include ellipsometry, quartz crystal microbalance, and mass spectrometry, which allow for the simultaneous growth of ALD films and the real-time characterization of the deposition process, important capabilities for thin-film R&D. Ultratech Cambridge NanoTech, 130 Turner Street, Building 2, Waltham, MA 02453, http://www.ultratech.com© 2015 American Institute of Physics.

Overlay errors, cut/block and line/space critical-dimension (CD) variations are the major sources of the edge-placement errors (EPE) in the cut/block patterning processes of complementary lithography when IC technology is scaled down to sub-10nm half pitch (HP). In this paper, we propose and discuss a modular technology to reduce the EPE effect by combining selective etching and alternating-material (dual-material) self-aligned multiple patterning (altSAMP) processes. Preliminary results of altSAMP process development and material screening experiment are reported and possible material candidates are suggested. A geometrical cut-process yield model considering the joint effect of overlay errors, cut-hole and line CD variations is developed to analyze its patterning performance. In addition to the contributions from the above three process variations, the impacts of key control parameters (such as cut-hole overhang and etching selectivity) on the patterning yield are examined. It is shown that the optimized altSAMP patterning process significantly improves the patterning yield compared with conventional SAMP processes, especially when the half pitch of device patterns is driven down to 7 nm and below.

With critical dimensions (CD) of integrated circuits shrinking to tens of nanometers, accurate metrology of three-dimensional feature shapes at different stages of the lithographic process becomes crucial to circuit performance. We propose Critical Shape Metrology (CSM), a CD-SEM-based technique that extracts accurate feature shape information from images obtained during routine in-line wafer inspection. Intensity profiles from CD-SEM images of known materials are compared in real time to profiles in an off-line generated Monte-Carlo SEM simulation library for the same materials with various model shapes. When the best match is found, metrics like bottom CD, top CD, sidewall angle, foot size and angle, and corner rounding can be obtained with high accuracy. The proposed technique takes advantage of the high resolution and throughput of low-voltage CD-SEMs, and does not require any additional tool calibration beyond the standard calibrations performed for conventional top-down CD metrology. While similar to optical scatterometry in concept, this technique allows for measurement of both isolated targets and dense arrays. Examples of performance on etched polysilicon and resist lines of different shapes are included and compared to SEM cross-sections and CD-AFM data.

The continued scaling for back-end-of-line (BEOL) for the sub-10 nm node poses significant challenges due to the shrinkage in dimensions and reduced Cu volume. Specifically for via, a clean interface between the underlying metal (Cu, Co) and Ta/TaN liner is required to reduce additional resistance-capacitance (RC) delays. Traditionally, fluoride based wet chemical systems are used to remove CuO x and post etch residues from the ultra-low k (ULK) dielectric sidewalls [1]. However, as the critical dimensions (CD) of BEOL integrated structures continue to shrink, the loss of RIE damaged low k dielectric material due to dilute HF (dHF) processing becomes a major concern. Furthermore, as Co metallization processes are being explored in interconnect structures, this necessitates an alternative to fluoride based solutions due to their incompatibility [2]. In this work, we are investigating an alternative alkaline based solutions with the addition of surfactants to prevent Cu/Co corrosion while effectively cleaning post etch residues with minimal CD loss. Some of the key parameters studied include solution concentration, oxygen levels, temperature and pH. Careful consideration was taken to adjust the solution pH by controlling the inhibitor concentration to enable Cu surface passivation while still effectively removing post etch residue (PER). As a first step, the Cu etch rates at a fixed alkaline solution concentration were measured using X-ray fluorescence (XRF) technique. Without corrosion inhibitor, Cu etch rates of 5 Å/min and 10 Å/min, respectively were measured at room temperature (RT) and 60 °C solution temperature. A significant reduction in etch rates of less than 2 Å/min was measured with the optimized inhibitor concentration in the alkaline solutions. There was no measurable change in ULK thickness for the pristine and damaged ULK films at RT, while approximately 5 Å loss at 60 °C was measured for the pristine film. Based on these results, optimized solution parameters such as concentrations, temperature, pH and process time, were developed. A transmission electron microscope (TEM) image of the metallized via structure is presented in Figure 1. It demonstrates that via structures remain intact with a continuous metal fill and no significant removal of the exposed underlying metal layer from the alkaline based cleans process. Additionally, the impact of cleaning was electrically evaluated by measuring resistance and yield using a metal-hardmask-trench-first-via-last (MHTFVL) scheme. Results indicate equivalence in comb-serpentine and via chain yields for the optimized alkaline solution compared to the dHF process. The electrical results for the normalized isolated via chain resistance values were within ~5% of the dHF baseline as shown in Figure 2. This demonstrates the ability of the alkaline based cleaning process to remove CuO x from the bottom of the via to achieve necessary inter-level resistance targets. In conclusion, alkaline based chemistries with the addition of surfactants are a suitable alternative to dHF based cleaning methods to remove RIE based polymer residues from high aspect ratio trench and via structures while maintaining stringent CD targets for sub-10 nm technology nodes. Acknowledgement: This work was performed by the Alliance Teams at various IBM and GLOBALFOUNDRIES Research and Development Facilities References [1] B. Peethala, F.W. Mont, S. Mollis, R. Knarr, B. L’lherron, C. Labelle, D. Canaperi, S. Siddiqui, Microelectronic Eng., 161, 98-103 (2016). [2] V. Kamineni et al., “Tungsten and Cobalt Metallization: A Material Study for MOL Local Interconnects”, International Interconnect Technology Conference (IITC), May 23 - 26 '2016, San Jose, California, USA. Figure 1

Replica-cell sensing schemes are commonly used in the read circuits of flash memories to provide the appropriate reference current across various process, voltage and temperature (PVT) conditions. However, process variation on the replica array causes fluctuations in the settling time and the value of the reference current across dies or wafers, especially in split-gate flash memories. A long settling time of reference current slows down the access time, and causes ringing on outputs. Fluctuation in the reference current produces various sensing margins, and decreases the yield, due to tail bits. A circuit-level technique for embedded flash memories, called pre-stable current sensing (PSCS), is proposed to reduce the fluctuation in access time and sensing margin, without additional masks or process steps. Experiments on fabricated flash macros (4 Mb, 2 Mb, 1 Mb, and 512 Kb) using a 0.25 mum embedded flash process demonstrate that PSCS achieves uniform access time across hundreds of samples. Additionally, PSCS works with a wide range of supply voltages (1.1-3 V).

The simplified electron energy flux (SEEF)model by which the backscattered energy distribution in the multilayered structure is calculated has been applied to the analysis of critical dimension (CD) variations caused by the thickness variations in copper interconnect. The SEEF model defines the reflection, downward transmission, and upward transmission of electron energy fluxes in each layer. Parameters of the SEEF model are expressed as functions of the depth from the substrate surface and are modified by the approximation in regard to the thickness variation. Using this approach, the process window for the dose and thickness variation has been analyzed quantitatively and the necessity of improving the process window has been confirmed especially at 45nm node and beyond. Moreover, a variation-aware proximity effect correction method, in which CD variations caused by process variations are reduced and dose margins for various patterns with the same linewidth are equalized, is proposed. The correction method improves the process window for isolated line pattern and 1:1 line-and-space pattern when the sixth wiring layer is fabricated.

This paper describes a simple and systematic etching approach for the preparation of smooth vertical bit line (BL), stacked with multiple layers of SiO2 (OX) and poly-Si (PL) films for the use in three-dimensional vertical gate (3DVG) NAND flash application. A successful shape evolution from tapered to acceptable BL profile with sub-10 nm critical dimension (CD) difference between bottom and top PL layers is performed by a recipe consisting of etch-trim-etch processing steps. This novel etch sequence is more advantageous than that of traditional simultaneous etch-deposition process for controlling profile shape of the multi-layer stack in the 3D NAND flash manufacturing.

In 3D NAND devices, the number of stacked layers dictates the storage capacity. In the fabrication of such devices, hole channels with a high-aspect ratio (HAR) are etched through these layers. The higher the aspect ratio becomes, the more difficulties the HAR etching faces. In this study, molecular dynamics simulation was performed to examine the etching of silicon dioxide (SiO2), silicon nitride (SiN), and oxide-nitride (ON) stacked layers by energetic fluorocarbon ions. Good agreement of etching yields obtained from the simulations and ion beam experiments was observed for the etching of SiO2 and SiN by CF3+ ions for the incident ion energy ranging from 200 to 2000 eV. As to the etching of the ON bilayer, the SiO2 and SiN layers were observed to be etched with their own etch rates at low ion incident energy. However, at sufficiently high incident ion energy, the oxide and nitride layers were mixed by energetic ion impact and the depth of the mixing layer exceeded the thickness of the top SiO2 layer thickness, resulting in a single etch rate limited by the etch rate of a much deeper underlying SiN material. This suggests that if the incident ion energy is high enough such that the thicknesses of the multilayers are lower than the ion penetration depth, the ON stacked layer exhibits a single etch rate determined by the mixed material of the oxide and nitride.

As the memory market becomes more diverse, the conventional memory hierarchies composed of Flash memory, DRAM and SRAM are now being asked to have various and segmented system to fill the gap between the current memory systems in terms of the cost and performance. The nonvolatile memory will upgrade the current memory subsystems and enable the stable system architectures that retain their state even when power is off. The emerging memories will not directly replace the existing memory (DRAM and Flash memory) but will make a new memory class. The attributes of STT-MRAM can lead to adopt in-memory computing architectures for the embedded memory solution SoC. In these circumstances, the accurate and scalable model of magnetic tunnel junction (MTJ) is required to accelerate the commercialization of STT-MRAM. In this thesis, after the MTJ basics is introduced as a storage element and the magnetic dynamics to utilize the electron spins as wells as the electron charges, the parallel and anti-parallel magnetization configuration is explained in terms of the band structure to understand the basic operation of the MTJ in memory cell. To demonstrate the viability of MTJ as a memory cell, the switching mechanism, reading/writing scheme, and some important parameters in STT-MRAMs such as TMR (Tunneling Magnetoresistance), Switching current (Ic), and Thermal Stability (Δ) are investigated. As a test vehicle of the technology, a set of RAM is designed in this research to show its efficiency and advantages of MTJ memory cell. As a first step of the design, the scalable model of a MTJ that accurately depicts the spin-transfer torque dynamic switching behavior of a MTJ is verified along with its bias voltage and Temperature dependency. The model integrates the physical models of static and dynamic behaviors; many experimental parameters are provided to see the process variations, especially temperature and bias voltage perspective. Based on the verified model, a set of RAM circuit is designed, and the designed STT-MRAM circuit's behavior and performances are analyzed to find the optimum tunnel magnetoresistance (TMR) ratio and switching performance. Of the compact model of the CoFeB/MgO PMA-MTJ (perpendicular magnetic anisotropy MTJ). The whole circuit was designed in a standard 45nm CMOS technology using MTJ. The measurement shows that the switching delay of MTJ increases by 5.5ns with growing tunnel barrier oxide (MgO) thickness from 0.85nm to 1.15nm. A bit longer delay for writing is observed as expected. The simulation shows a trade-off between memory access time and MTJ area as the switching delay of MTJ decreases by 6.5ns when the MTJ area increases from 1010nm to 4040nm. For reading operation of the memory, the conventional sense amplifier circuit is employed to detect the stored bit-cell. In the reading peripheral circuits including sense amplifier, the fixed reference voltage (0.9V) is used to simplify the analysis. The reading operation and peripheral block of memory circuits is verified successfully with read access time of 1.47ns.--Author's abstract

Flash memory cells typically undergo a few thousand Program/Erase (P/E) cycles before they wear out. However, the programming strategy of flash devices and process variations cause some flash cells to wear out significantly faster than others. This paper studies this variability on two commercial devices, acknowledges its unavoidability, figures out how to identify the weakest cells, and introduces a wear unbalancing technique that let the strongest cells relieve the weak ones in order to lengthen the overall lifetime of the device. Our technique periodically skips or relieves the weakest pages whenever a flash block is programmed. Relieving the weakest pages can lead to a lifetime extension of up to 60% for a negligible memory and storage overhead, while minimally affecting (sometimes improving) the write performance. Future technology nodes will bring larger variance to page endurance, increasing the need for techniques similar to the one proposed in this work.

In this publication an alternative approach to investigations of bacterial growth is proposed. Contrary to the conventional physical methods it is based on enzyme activity detection. The procedure for real-time and on-line monitoring of microbial ureolytic activity (applied as a model experimental biosystem) in the flow analysis format is presented. The developed fully-mechanized bioanalytical flow system is composed of solenoid micropumps and microvalves actuated by Arduino microcontroller. The photometric detection based on Nessler reaction is performed using dedicated flow-through optoelectronic detector made of paired light emitting diodes. The developed bioanalytical system allows discrete assaying of microbial urease in the wide range of activity up to 5.4 U mL−1 with detection limit below 0.44 U mL−1, a high sensitivity in the linear range of response (up to 200 mV U−1 mL and relatively high throughput (9 detection per hour). The proposed differential procedure of measurements (i.e. a difference between peaks register for sample with and without external addition of urea is treated as an analytical signal) allows elimination of interfering effects from substrate and products of biocatalysed reaction as well as other components of medium used for microbial growth. The developed bioanalytical system was successfully applied for the control of growth of urease-positive bacteria strains (Proteus vulgaris, Klebsiella pneumoniae and Paracoccus yeei) including examination of effects from various microbial cultivation conditions like temperature, composition of culture medium and amount of substrate required for induction of bacterial enzymatic activity. The developed bioanalytical flow system can be applied for metabolic activity-based estimation of parameters of lag and log phases of microbial growth as well as for detection of decline phase.