Memory technology: process and cell architecture

Impact of resistive paths on NVM array reliability: Application to Flash & ReRAM memories

With an explosive growth of data generated by various applications, one of the most important topics of the current era is to increase the storage capacity. The evolution from 2D planar NAND to 3D NAND enables the development of high-density storage by increasing the number of stacked word-lines (WLs) in a smaller footprint. The industry has moved beyond 96-stacked-WL and achieved a 128-stacked 3D NAND. A 128-stacked 3b/cell 3D NAND with a density of 7.8Gb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was reported recently, based on a peripheral circuit under cell array (PUC) structure [1]. Nevertheless, due to the constant demand for increased density, 3D NAND faces the following challenges [2,3]: (1) a reduced PUC area due to an increasing WL stack, (2) increased load due to a higher number of stacks and a reduced spacing between WLs, (3) rising WL-channel capacitance due to an increasing number of strings, and (4) variation in the RC delay between WLs due to the non-uniformity of plug critical dimension (CD). Not only do these problems limit the density improvement of 3D NAND, but they also increase the WL rise time, which degrades read and write performance. This paper proposes the following techniques to overcome these challenges: (1) a 12-stage page buffer (PB) with one-to-one (1:1) PBUS(PB to cache connection bus), (2) a variable stage and frequency charge pump with a boosted local pump, (3) center X-decoder (XDEC) and half-plane activation, (4) an unselected string boosting scheme, and (5) adaptive WL overdrive (OVD). By applying these techniques, we achieved a density of 10.8Gb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 176stacked 3D NAND using 3b/cell.

The adoption of tier stacking (dual deck) leads to increasingly high aspect ratios and poses challenges in controlling overlay, tilt, and misalignment in the manufacturing processes for next generation 3D NAND devices. In this work we address metrology challenges such as tilt and overlay separation, measurement robustness influenced by process variation, and nonlinearity of spectral response to asymmetries. We show that Mueller measurement can separate overlay and tilt signals through distinct spectral response analyzed by a machine learning method with reference data. To reduce asymmetry measurement errors caused by process variation such as critical dimension (CD) and thickness changes, we propose and demonstrate improvement of tilt measurements on blind test wafers by feeding forward CD measurement results to the analysis of tilt signal. We also investigate nonlinear regression and show its capability to extend overlay measurement limit from linear response range, ±0.25pitch, to ±0.43pitch. In addition, for small structural asymmetries introduced by channel hole tilt, test RMSE is reduced by 20–40% from nonlinear regression alone or combined with CD feed-forward. We demonstrate that spectroscopic Mueller matrix measurements, paired with advanced machine learning analysis, provide nondestructive and accurate measurement of tilt, overlay, and misalignment for 3D NAND devices with high throughput and fast recipe creation.

We propose a novel 3-D vertical floating-gate (FG) nand Flash memory cell array with a novel electrical source/drain (S/D) technique using extended sidewall control gates (ESCGs). A cylindrical FG structure is implemented to overcome the reliability issues of charge-trap-type cells. A novel electrical S/D layer by the ESCG structure also allows enhancement-mode operation. With this novel structure, we successfully demonstrate normal Flash cell operation with high-speed programming and superior read currents due to both the increase in coupling ratio and the use of low resistive electrical S/D technique by device simulation. Moreover, we found that the 3-D vertical Flash memory cell array with the novel electrical S/D technique had less interference with neighboring cells by about 50% in comparison with the conventional 3-D vertical FG nand cell array without an ESCG. Above all, the proposed cell array is one of the candidates for a Terabit 3-D vertical nand Flash cell array with high-speed read/program operation and high reliability.

Recently, storage systems have observed a great leap in performance, reliability, endurance, and cost, due to the advance in non-volatile memory technologies, such as NAND flash memory. However, although delivering better performance, shock resistance, and energy efficiency than mechanical hard disks, NAND flash memory comes with unique characteristics and operational constraints, and cannot be directly used as an ideal block device. In particular, to address the notorious write-once property, garbage collection is necessary to clean the outdated data on flash memory. However, garbage collection is very time-consuming and often becomes the performance bottleneck of flash memory. Moreover, because flash memory cells endure very limited writes (as compared to mechanical hard disks) before they are worn out, the wear-leveling design is also indispensable to equalize the use of flash memory space and to prolong the flash memory lifetime. In response, this paper surveys state-of-the-art garbage collection and wear-leveling designs, so as to assist the design of flash memory management in various application scenarios. The future development trends of flash memory, such as the widespread adoption of higher-level flash memory and the emerging of three-dimensional (3D) flash memory architectures, are also discussed.

Taiwanese memory packaging and testing factories include Powertech, ChipMOS, ASE, SPIL, Walton and FATC. The global three first tier giants, Samsung Electronics, Hynix and Micron, have predicted that the DRAM market in 2014 will be more stable. With the three-giant monopolization taking shape, the strategic alliance and corresponding excess profits of back-end packaging factories are expected to be gradually improved. The computex new products covering semiconductors/components, green energy efficiency, Fujitsu wafer manufacturing, packaging and testing, and memories, etc. are going to take to the stage and Taiwanese IC design related firms are scrambling to grab any business opportunities. All of these will be sensationally showcased at the Taipei International Computer Show. 3D NAND will be the future trend and price competition will be the challenge of respective factories. SK Hynix and Samsung will race to launch green semiconductors, with which the information center trade will turn out to be the biggest customer. NAND Flash will march into the corporate storage market and the conventional storage trade will face a greater challenge. Fujitsu is optimistic about the demand for 4G transistors in 2014, in which the demand will be much stronger in the second half. Samsung and STMicroelectronics will expand its contract manufacturing of 28nm FD-Soi. SPIL, a packaging and testing factory, will devote its efforts to becoming the world 2nd largest packaging factory. As indicated by its president Lin Wen-Bo, as sustained by the popularity of smart phones, the demand for advanced semi-conductor packaging will continue to remain strong in 2014 which will lead to continuation of the profits. According to Korea, Times, the world number one technology giant Samsung has boasted its memory chip business, but the business has now been put to the tough test. For green energy efficiency and Taiwan's solar power integration, Morris Chang will be the key decision maker. Google will invest 600 million US dollars in the data center at Lenoir of North Carolina, and participate in foundry services. Apple's release of orders will offer more business opportunities, with which production of smart phones and components will expand.

The increasing usage of flash memory in mobile applications is pushing the scaling limit of Flash memory technology. This paper presents a systematic scaling methodology, architecture, optimization strategy, and performance of sub-90 nm split-gate flash memory cells. The device simulation results show that the split-gate cells can be scaled to 90 nm node and below using shallow source/drain junctions and a highly localized source-halo in conjunction with channel engineering. Using properly optimized technology parameters, sub-90 nm cells with tolerable leakage current and efficient time-to-program and time-to-erase can be achieved

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Disturb failures are considered the most predominant failure mode in flash memories. Disturb faults are highly dependant on the core memory cell structure, manufacturing technology, and array organization and operation. In this paper, we develop appropriate fault primitives for all possible disturb faults in flash memories. Further, we analyze the origins of such disturbs and propose a method that uses cell structure and array organization information to identify the relevant disturbs to create reduced list of faults. As an example, the method was used to create a minimized faults list for NOR and NAND flash memory arrays. Moreover, we show how the reduced fault list developed can be used to devise more efficient test algorithms.

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This paper provides an overview of 3D NAND Flash memory architecture and a comprehensive study on various array decoding methods of vertical gate (VG) NAND Flash. A certain memory density may be achieved by any array architecture but with different numbers of stacking layers. A smaller pitch allows the achieving of high density at reasonable number of stacked memory layers (≤ 32) and thus potentially offers lower cost. VG NAND has good pitch scalability thus is very attractive. On the other hand, it is more difficult to decode the bit line in a VG architecture, thus decoding innovations are required for a compact array architecture design. This paper provides a systematic comparison of four different decoding methods of VG NAND. Performance of the TFT BE-SONOS device used in 3D VG NAND is also addressed.

3D NAND memory, featuring vertically stacked memory cells to enhance storage density and performance, serves as a critical component in modern data storage solutions and AI applications. In this paper, we investigated the electrical impact of memory hole (MH) mis-formation defects in a multi-tier three dimensional (3D) NAND memory technology. Despite being confined to local word lines (WLs) and source lines (SLs), such defects cause a global impact to all the memory cells in the same plane by slowing down their program speed. Specifically, the bit line potential of victim cells is disturbed when quick pass write (QPW) program technique is implemented. Such disturb originates from the interaction between source line and global bit line through the aggressor memory cells. Based on the failure mechanism, several approaches were proposed to improve the screen efficiency for these defects, which could otherwise become latent system failures.

In this paper we describe and evaluate two possible architectures using 3D DRAMs and PCMs in the processor memory hierarchy. We explore using (a) 3D DRAM as main memory with PCM as backing store and (b) 3D DRAM as the Last Level Cache and PCM as the main memory. In each of these configurations, since the proposed main memories are significantly faster than today's off-chip 2D DRAMs for main memory and either flash memory based SSDs or magnetic hard drives for secondary storage, we will introduce hardware assistance for virtual to physical address translation and to speed up page-fault handling. We use Simics, a full system simulator and benchmarks from both SPEC 2006 and OLTP suites to evaluate our designs. Our experiments measure energy consumed and execution performance; we use CACTI for obtaining energy and latency values for our memory configurations.

In order to overcome the limitation of cell area of 4F/sup 2/ per bit in conventional NAND flash memory cells, stacked-surrounding gate transistor (S-SGT) structured cell is proposed. This newly structured cell achieves a cell area of 4F/sup 2//N per bit, where N is the number of stacked memory cells in one silicon pillar, without using multibit per memory cell technology. The S-SGT structured cell consisting of two stacked memory cells in one silicon pillar achieves a cell area per bit of less than 50% of the smallest reported NAND structured cell. The novel S-SGT structured cells are fabricated by vertical self-aligned processes using a 0.2 /spl mu/m design rule. The S-SGT structured cell can be programmed and erased by uniform injection and uniform emission of Fowler-Nordheim (F-N) tunneling electrons over the whole channel area of the memory cell, respectively, which is the same program and erase mechanism as in conventional NAND structured cell. This high performance S-SGT structured cell is applicable to high-density nonvolatile memories for 16 G/64 G bit Flash memories and beyond.

The lack or incorrect implementation of storage device privacy and secret-related information erasure methods will cause serious security risks for personal privacy and national construction security. Although information erasure based on overwrite for magnetic storage media is relatively mature, it is difficult for these mature technologies to be directly used in the currently widely used NAND flash memory due to its complex structure and other reasons, and its security is in doubt. The recycling industry of waste electronic equipment, mainly smart phones, is facing the problem of lack of information security clearance. In addition to the hidden dangers of information security, this situation also leads to the low recovery rate of waste electronic equipment, which leads to potential waste of resources and environmental pollution. In view of the above problems, this article reviews the information erasure for NAND flash based on the overwrite technology to support the in-depth research of the information erasure technology. At first, it introduces the definition and classification of information erasure. Then, the characteristics of NAND flash memory is analyzed. Thirdly, it summarizes the information erasure technology based on overwriting. And the research difficulties and application difficulties of information erasure technology for NAND flash memory is discussed and analyzed. Finally, conclusions and prospect the future research direction of overwrite-based information erasure technology for NAND flash are given out.