Clocking for correct functionality on wave pipelined circuits

The existing state of the art lock/out-of-lock detection schemes used in PLL (Phase lock loop) suffers from process, voltage and temperature (PVT) variations and has limited accuracy especially in fractional PLL mode of operation. Moreover, the schemes are not suitable to detect both lock and out-of-lock condition accurately. This paper describes a novel mixed signal scheme which incorporates detection of both lock and out-of-lock conditions of a PLL. The scheme covers integer and fractional PLL modes of operations and programmable to generate lock condition to a very high accuracy. Furthermore, this digital detection scheme is not prone to process, voltage and temperature variations.

The CMOS based memories are facing major issues with technology scaling, such as decreased reliability and increased leakage power. A point will be reached when the technology scaling issues will overweight the benefits. For this reason, alternate solutions are being proposed in literature, to possibly replace charge based memories. One of the most promising of these solutions is the spin-transfer-torque magnetic random access memory (STT-MRAM). To evaluate the viability of such solution, one must understand how it behaves under the effect of the various reliability degradation factors. In this paper we propose a methodology which allows for fast reliability evaluation of an STT-MRAM cell under process, voltage, and temperature variations. Our proposed method allows for a sensitivity analysis which will show the designer/test engineer which is the main reliability concern of a certain design. The method is general, and it can be applied to any memory design.

Process, voltage and temperature (PVT) variations in emerging ultra-deep submicron (UDSM) technology nodes critically affect device performances and limit further scaling of such devices based on Moore's law. This paper proposes CNFET-based design of robust Schmitt trigger circuits, which outperform their CMOS counterparts in terms of mean values as well as variabilities of all considered design metrics. Popular Schmitt trigger designs are investigated and a comparative analysis is carried out based on Monte Carlo simulations in an HSPICE environment, using the 16-nm CMOS Predictive Technology Model (PTM), to choose the designs with best performance in terms of variability of design metrics such as power, power-delay product (PDP) and hysteresis width. These are then re-designed with corresponding optimized devices using the experimentally validated Stanford University CNFET model. The proposed CNFET-based circuits provide a 9.9×, 11.8× and 22× improvement in power, PDP and hysteresis width variability respectively, while also providing better noise immunity through increased hysteresis widths, thus demonstrating their superiority to CMOS circuits in all respects at highly scaled technology nodes.

In this paper, we proposed a Ring Time-to-Digital Converter (RTDC)-based Capacitance-to-Digital Converter (CDC) that is insensitive to PVT variation. The proposed CDC embeds a Capacitance-to-Time Converter (C2T) with high linearity, leveraging a parasitic elimination technique to counteract environment changes. Thanks to the ring structure of RTDC, the presented CDC has theoretically infinite detection range. However, RTDC suffers from the process, voltage and temperature (PVT) variation, compromising its dynamic range. This paper proposed a new architecture that matches the current sources of the front-end and delay cells in the RTDC. Therefore, the front-end and RTDC have the same PVT response, leading to an inherent-PVT-stabilized feature. The proposed CDC was implemented in a 40-nm LP CMOS process. Simulation results show that it achieves 0.55fF resolution under 10pF parasitic capacitance and it covers 3.75-64pF capacitance detection range, with a 0.56pJ/conversion-step figure of merit and a maximum 20us conversion time.

This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors and have high boosting efficiency with sharp output performance. Comparative evaluations with existing bootstrapped driver circuits are reported. Simulation results are derived by HSPICE tool with predictive technology model (PTM) bulk CMOS process fabrication at 32 nm technology node. The ability of large leakage reduction makes this driver superior as compared to active drivers. An average of 96.97% leakage current is saved at nominal ultra-low voltage of 0.15 V. Monte-Carlo analysis indicates that the proposed bootstrapped driver has less sensitivity of PVT variations. The power consumption and delay sensitivities are reduced by 10 × and 4.12 × as compared to conventional circuit.

For high system performance in VLSI chips dynamic CMOS logic circuit techniques are used. As continue scaling down the dimension of transistors parameter variation becomes a serious issue in very deep sub-micron regime. The overall performance of any logic circuit reduces by increasing leakage current and variability of parameters in scaled device. To overcome the variability issue in sub-micron regime the design must be aware of variations. In this paper DOIND logic approach is proposed for domino logic to analyze the variability issue. This approach reduces leakage current as well as it reduces the variability issue with minimum delay penalty. Various process, voltage and temperature (PVT) variations are analyzed at 70 nm technology node for a domino logic and DOIND logic buffer using tanner EDA tool. Simulation result shows that DOIND approach has less affect of PVT variations as compare to domino logic circuit.

In this paper, a 6.78MHz GaN-based full-bridge active rectifier with enhanced power conversion efficiency (PCE) and voltage conversion ratio (VCR) is proposed. The design features a bootstrap driver to actively switch the high-side GaN transistors, as well as real-time calibration loops to automatically compensate the circuit delays in the low-side control paths, such that the PCE and VCR are maximized with eliminated reverse current and optimal conduction time. The proposed active rectifier is designed and simulated in a 180nm BCD process, and verified under process, voltage and temperature (PVT) variations with power capacity from 20 to 180 W. Thanks to the proposed calibration loops, up to 25% and 20% PCE and VCR improvements, respectively, are observed under various PVT and loading conditions, with a peak PCE of 94.1% at 90-W output power and a peak VCR at 98% at 20-W output power.

High resolution time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) with compensated process voltage and temperature (PVT) variations

This demo demonstrates the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from - 40 ° C to 125 ° C confirmed the effectiveness of the proposed approach to compensate even for severe process, voltage and temperature (PVT) variations.

This paper presents a spread-spectrum clock generator (SSCG) based on voltage-controlled oscillator (VCO) direct modulation. An auxiliary frequency-locked loop has been employed to guarantee a stable and accurate spread ratio under the variations of process, voltage and temperature (PVT). Besides, the spread ratio can be programmed via different counting value in the auxiliary loop. Implemented in UMC 0.18-μm CMOS technology, the SSCG achieves a 9.97 dB reduction in the peak power spectrum with 0.5% spreading at 31.56 kHz modulation frequency. The die area of the SSCG is 0.42×0.45mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits ( rms ) for high-performance ADCs. The key idea is twofold: a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, b) performing a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8V 0.18µm and 1.2V 90nm).

This paper presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 4 ps, fabricated in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. To achieve the low resolution, the delay elements are implemented using a new interlocked interpolation technique to reduce the Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) error. The delay line is placed inside a Delay Locked Look (DLL) to compensate for Process, Voltage and Temperature (PVT) variations- and variations due to ionizing radiation.

An ultra wideband (UWB) low nose amplifier (LNA) is presented in this paper. It is designed to operate in the complete range (3-10 GHz) as defined by the US Federal Communications Commission (FCC) using the 130 nm CMOS technology process. The main goals of the design are low noise, high linearity and low variance of the gain over the operating frequency range. To achieve this, the two stage topology is used that yields the following results: input reffered intercept point (IIP3) of up to 2.30 dBm and forward gain (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> ) of 14.73 dB with the variation of ±1.15 dB over the mentioned range. Maximum noise factor (NF) is less than 4 dB and the input return loss (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> ) is less than -10 dB. The power dissipation is 32.50 mW for the supply voltage of 1.20 V. The process, voltage and temperature (PVT) variations are analysed and the results are discussed in the paper. The results given are obtained through the schematic level simulations using Spectre Simulator from Cadence Design System.

A 6.6 mW 1.25–2.25 GHz low phase noise PLL frequency synthesizer based on wide tuning range Class-C VCO

Carbon nanotube field-effect transistor (CNTFET) is envisioned as a promising device to overcome the limitations of traditional CMOS based MOSFETs due to its favourable physical properties. This paper presents a novel six-transistor (6T) static random access memory (SRAM) bitcell design using CNTFETs. Extensive validations and comparative analyses are carried out with the proposed SRAM design using SPICE based simulations. We show that the proposed CNTFET based SRAM has a significantly better static noise margin (SNM) and write ability margin (WAM) compared to a CNTFET-based standard 6T bitcell, equivalent to isolated read-port 8T cell based on CNTFET, while consuming less dynamic power. We further demonstrate that it exhibits higher robustness under process, voltage and temperature (PVT) variations when compared with the traditional CMOS SRAM cell designs. Furthermore, metallic CNTs removal technique is used considering metallic tolerance to make the proposed SRAM design more reliable.