STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations

Random Access Memories: Magnetic

In recent years, the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under today aggressive technology scaling requirements, the STT-MRAM is affected by process variability and aging phenomena, making reliability prediction a growing concern. In this paper, we provide a methodology for predicting the reliability of an STT-MRAM based memory at block level for different block sizes and access rates. The proposed methodology also allows for an exploration of required error correction capabilities as function of code word size to achieve the desired reliability target for the memory under study.

The existing state of the art lock/out-of-lock detection schemes used in PLL (Phase lock loop) suffers from process, voltage and temperature (PVT) variations and has limited accuracy especially in fractional PLL mode of operation. Moreover, the schemes are not suitable to detect both lock and out-of-lock condition accurately. This paper describes a novel mixed signal scheme which incorporates detection of both lock and out-of-lock conditions of a PLL. The scheme covers integer and fractional PLL modes of operations and programmable to generate lock condition to a very high accuracy. Furthermore, this digital detection scheme is not prone to process, voltage and temperature variations.

One of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low area, low power consumption, and good scaling capability. In this paper, we estimate the STT-MRAM cell reliability under fabrication- and aging-induced process variability, by evaluating its failure probability. We analyze the effect of control voltage tuning on the fresh and aged cell failure probabilities and, as a result, we propose a power- and aging-aware circuit level variability mitigation technique based on control voltage tuning. We observed that increasing the values of control voltages, the cell failure probability is reduced at different extends (according to the control voltage under variation), but also that the power consumption is increased. As a result, we have identified the control voltage with the highest impact on the fresh cell reliability, and on the endurance of the cell under study. Subsequently, by performing a power/reliability trade-off analysis, the appropriate value of this control voltage is determined.

Spin-transfer-torque magnetic random-access memory (STT-MRAM) is a proven technology for embedded non-volatile memory applications. The backhopping phenomena in STT-MRAM, whereby the resistance of the device oscillates under higher current, has been recently explored for emerging spiking neural network applications. We report a detailed characterization of backhopping in foundry compatible STT-MRAM having ~15kb bit-cell arrays by analyzing the behavior of backhopping spike rate versus applied current and temperature. Our study shows that the backhopping in STT-MRAM exhibits the Poisson statistics with a controllable spike rate with current that displays three regimes: non-backhopping, exponential and linear. This mimics the behavior of a rectified linear unit (ReLU) neuron, a commonly used activation function in deep learning models. A spiking neural network (SNN) communication channel is simulated using the derived statistics and a first principles mathematical framework to analyze the reliability performance of backhopping-based SNN in terms of trading-off the accuracy and applied current.

Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) is emerging as a leading candidate for a variety of embedded memory applications ranging from embedded NVM to working memory and last level cache. In this paper, we review recent breakthroughs that have brought perpendicular STT-MRAM to the cusp of mass production.

Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology because of its various advantageous features such as scalability, non-volatility, density, endurance, and soft-error immunity. However, high write energy and long write latency are the major obstacles for this technology. The long write latency of the STT-MRAM is primarily due to two reasons. First, the bit-cell switching is asymmetric, which means that one write direction is significantly slower than the other. Second, the stochastic switching behavior of the bit-cell mandates a significant margin for a target write error rate (WER). In this paper, we propose static and dynamic circuit-level techniques to reduce the overall write latency. The static technique reduces the impact of write asymmetry by increasing the write current only for the slow writes. The dynamic technique additionally targets the write margin by dynamically increasing the write current in a stepwise manner to mitigate the negative impact of the stochastic switching behavior. Experimental results show that our proposed dynamic method can reduce the overall write latency by 71% while maintaining the same WER. Applying this technique to a 512 kB L2-cache of a microprocessor improves its performance by 11% and saves energy by 10% on average.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is an emerging memory technology, which is seen as a promising replacement for CMOS based on-chip memories. It has several distinctive advantages such as nonvolatility, high endurance, high density, CMOS compatibility and scalability among others. However, retention failure has emerged as a major reliability concern for this technology due to the large variations in retention time because of process variations and temperature effects. The conventional solution to mitigate retention failures is to use scrubbing at regular intervals to prevent accumulation of errors, based on the worst case retention time of the memory array. But this leads to large performance and energy overheads. In this work, we propose a process variation and temperature aware scrubbing technique, where we cluster the cache lines into different groups based on their retention times and use different scrubbing intervals for each of these groups. In addition, the scrubbing interval is adjusted at run-time based on the operating temperature, to guarantee target error rate requirements. Our results show that for a 512KB cache, a group size of 4 can reduce the performance and dynamic energy overheads of scrubbing by 97%, under the same error rate constraint.

With integration density on-chip rocketing up, leakage power dominates the whole power budget of contemporary CMOS based memory, especially for SRAM based on-chip cache. A few non-volatile technologies especially magnetic random access memory (MRAM) technologies are proposed to deal with this issue. Among them, spin transfer torque (STT) MRAM is a possible candidate for future on-chip cache design. However, as the cache capacity keeps growing, STT-MRAM suffers the bottlenecks on both operation speed and power efficiency. In this context, a new NAND-like spin orbit torque (SOT)-based MRAM, NAND-SPIN, which combines the high density of the STT-MRAM and the high performance of the SOT- MRAM has been proposed. Thanks to these benefits, NAND-SPIN could be more suitable for the future large capacity application. In the paper, we evaluate the NAND-SPIN for on-chip cache design in terms of performance, area and power consumption. The runtime system level experimental results show that NAND- SPIN has higher performance/power efficiency compared to SRAM, STT-MRAM and SOT-MRAM, especially in the large capacity situation.

Spin transfer torque magnetic random access memory (STT-MRAM) is one of the most promising new non-volatile memory technologies. Recently, STT-MRAM has become popular as a DRAM alternative in main memories particularly for tablets and palmtop computers in part due to its non-volatile properties and potential for improved device scalability. However, STT-MRAM is well known for its asymmetric access properties and considerable attention has been applied to the device, circuit, and architecture designs to mitigate its write energy concerns. In this work, we propose a new method to reduce the write energy consumption using a combination of pulse width scaling and error correction coding schemes for STT-MRAM main memories. The introduced methodology works by dynamically adjusting the pulse width based on the compressibility of the written data. We evaluate the efficiency of the proposed method on Android applications. Experimental results show an average improvement of more than 10% in the write energy consumption, in addition to the 46% reduction achieved by compression.

Spin transfer torque magnetic random access memory (STT-MRAM) is a promising candidate for next generation memory as it is non-volatile, fast, and has unlimited endurance. Another important aspect of STT-MRAM is that its core component, the nanoscale magnetic tunneling junction (MTJ), is thought to be radiation hard, making it attractive for space and nuclear technology applications. However, studies on the effects of ionizing radiation on the STT-MRAM writing process are lacking for MTJs with perpendicular magnetic anisotropy (pMTJs) required for scalable applications. Particularly, the question of the impact of extreme total ionizing dose on perpendicular magnetic anisotropy, which plays a crucial role on thermal stability and critical writing current, remains open. Here we report measurements of the impact of high doses of gamma and neutron radiation on nanoscale pMTJs used in STT-MRAM. We characterize the tunneling magnetoresistance, the magnetic field switching, and the current-induced switching before and after irradiation. Our results demonstrate that all these key properties of nanoscale MTJs relevant to STT-MRAM applications are robust against ionizing radiation. Additionally, we perform experiments on thermally driven stochastic switching in the gamma ray environment. These results indicate that nanoscale MTJs are promising building blocks for radiation-hard non-von Neumann computing.

The Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) has been identified, by the International Technology Roadmap for Semiconductors (ITRS), as one of the most promising emerging technology. Different works handled the retention and reliability of STT-MRAM. However, to the best of our knowledge, the impact of a pulsed laser beam on STT-MRAM reliability and security has not been investigated so far as proposed in this paper. Since STT-MRAM are Back-end Of Line devices, we exposed the bit cells from the front-side to a 1064 nm wavelength laser pulse. The devices are electrically characterized (switching conditions between the two logical states) before and after the laser irradiation. The main result of this study is the demonstration of a resistance switching from Anti-Parallel (AP) to Parallel (P) state after the laser irradiation. That is how data integrity was altered by this irradiation, flipping the bit stored in this memory.

The emerging spin-transfer torque magnetic random-access memory (STT-RAM) has attracted a lot of interest from both academia and industry in recent years. It has been considered as a promising replacement of SRAM and DRAM in the cache and memory system design thanks to many advantages, including non-volatility, low leakage power, SRAM comparable read performance and read energy consumption, higher density than SRAM, better scalability than conventional CMOS technologies, and good CMOS compatibility. However, the disadvantages of STT-RAM, such as higher write energy and longer write latency than SRAM, also bring design challenges. This paper introduces state-of-the-art architectural approaches to adopt STT-RAM in the cache and memory system design by taking advantage of the opportunities brought by STT-RAM as well as overcoming the challenges. © 2016 IEEE.

Spin transfer-torque Magnetic Random Access Memory (STT-MRAM) is expected to play a major role in the future development of information and communication technologies. One of the drivers of the technology is the non-volatile character of this type of memory that allows to reduce the energy consumption compared to SRAM or DRAM. [1]Globally, we are seeking to develop technologies that help reduce carbon emissions. However, the nature of the materials involved in such technologies is also a concern both in terms of environmental impact and supply risk. [2,3]MRAM contains several materials classified as critical raw materials, in particular by the European Union (EU), being of high importance to the EU economy and whose supply is classified of high risk. [4]In order to improve the stability of the reference layer whose magnetic configuration has to remain fixed during the lifetime of the memory, a synthetic antiferromagnet (SAF) is typically used. This SAF structure is normally based on Co/Pt or Co/Pd multilayers antiferromagnetically coupled through a thin Ru layer. Platinum Group Metals (PGMs) have been classified as critical materials with high supply risk. In addition, obtaining these metals in their refined form requires extensive amounts of energy and CO2 emissions due to the low initial ore concentration.In this work, an assessment of the impact of the substitution of the Pt required in STT-MRAM for the SAF layer has been made. Alternative solutions can be envisaged such as the use of multilayers based on Co/Ni exhibiting perpendicular anisotropy [5]. A second more challenging approach based on the use of perpendicular shape anisotropy (PSA) does not rely on the use of PGMs. However, this PSA based approach is more challenging from technological point of view due to the requirement of a strict control of the cell diameter at sub-20nm dimensions during the etching process. The possibility of using Co/Ni multilayers for the SAF of MRAM has been already demonstrated [6,7]. We have observed how similar properties to Co/Pt SAF can be obtained by using Co/Ni multilayers (Figure 1). Our study has the added advantage of using a seed layer free of Hf, used in some previous studies to promote the required (111) texture for the Co/Ni multilayers growth [6,7]. Hf is also a material classified as critical and whose production is strongly concentrated in two countries, France and USA. In our study a Cu seed layer is used allowing for more diverse production sources.An evaluation of the environmental (energy and global warming potential) and economic impact of the substitution has been performed. Strong improvements in both economic and environmental aspects can be achieved by the substitution. However due to the tiny amounts of PGM materials used in STT-MRAM, in comparison to the mass of the silicon wafer itself, the environmental impact and price of the silicon wafer on which these memory devices are grown is much higher as shown in Figure 2. Our conclusion is that more attention should be focused on the process of fabrication of silicon wafers or find a substitution to this type of wafers whenever possible.Nevertheless, the high supply concentration of Pt as four mining companies represent the 80% of the global production [8] makes the presence of these alternatives a key aspect to ensure the survival of the technology in case of supply disruptions. **

As the process node is scaled down, the spin-transfer-torque magnetic random-access memory (STT-MRAM) exhibits higher memory density than the static random-access memory (SRAM), making it one of the more promising successors of the low-level on-chip cache memory. However, the low read margin (RM) of the magnetic tunnel junction (MTJ) in STT-MRAM can limit the achievable read accuracy. We implemented 2-bit channel quantization for error-correcting code (ECC) schemes and explored the trade-offs between improved read accuracy and factors such as circuit area, power consumption, and latency. The proposed quantization scheme consists of a sensing amplifier-based 2-bit quantizer and MTJ resistor-based soft-decision thresholds. Compared to 1-bit channel quantization using the Bose–Chaudhuri–Hocquenghem (BCH) code, the proposed 2-bit quantization architecture achieves a fourfold reduction in frame error rate (FER) from 8.0×10−4 to 2.0×10−4 when paired with polar codes and successive cancellation (SC) decoding. Additionally, this approach results in decoding complexity that is only 1/13th of that required for BCH at a 0.7 code rate.