Data Parallel Address Architecture

Data-parallel memory systems must maintain a large number of outstanding memory references to fully use increasing DRAM bandwidth in the presence of rising latencies. Additionally, throughput is increasingly sensitive to the reference patterns due to the rising latency of issuing DRAM commands, switching between reads and writes, and precharging/activating internal DRAM banks. We study the design space of data-parallel memory systems in light of these trends of increasing concurrency, latency, and sensitivity to access patterns. We perform a detailed performance analysis of scientific and multimedia applications and micro-benchmarks, varying DRAM parameters and the memory-system configuration. We identify the interference between concurrent read and write memory-access threads, and bank conflicts, both within a single thread and across multiple threads, as the most critical factors affecting performance. We then develop hardware techniques to minimize throughput degradation. We advocate either relying on multiple concurrent accesses from a single memory-reference thread only, while sacrificing load-balance, or introducing new hardware to maintain both locality of reference and load-balance between multiple DRAM channels with multiple threads. We show that a low-cost configuration with only 16 channel-buffer entries achieves over 80% of peak throughput in most cases.

In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a single thread) are issued simultaneously to multiple functional units, and these instructions can begin execution unless there are functional unit conflicts. This parallel execution scheme greatly improves the utilization of the functional unit. Simulation results show that by executing two and four threads in parallel on a nine-functional-unit processor, a 2.02 and a 3.72 times speed-up, respectively, can be achieved over a conventional RISC processor.Our architecture is also applicable to the efficient execution of a single loop. In order to control functional unit conflicts between loop iterations, we have developed a new static code scheduling technique. Another loop execution scheme, by using the multiple control flow mechanism of our architecture, makes it possible to parallelize loops which are difficult to parallelize in vector or VLIW machines.

In previous studies, we developed innovative anti-loosening bolts and nuts with a double-thread structure (denoted DTB-IIC) composed of coaxial single and multiple coarse threads. It was also experimentally proven that the DTB-IIC has high anti-loosening performance. In this study, we analytically and experimentally investigated the effects of multiple thread groove depths and rolling methods on the thread rolling formability of DTB-IIC fasteners. The bottom rise rate of the multiple-thread groove was set in three ways of 50%, 60%, and 70%. As the depth of the multiple thread groove became shallower, peeling on the thread surface was suppressed and the high temperatures produced by thread rolling decreased significantly, but the loosening resistance against vibration clearly decreased. We compared three typical mass production processes for bolts: the round die method, the flat die method, and the planetary method, with the bottom rise rate set at 50%. It was found that the flat die method had the best rolling formability in terms of screw-thread shape and surface quality. A Finite element simulation consistently reproduced the deformation process of the complex DTB-IIC thread and revealed that the material shear flow due to over-rolling led to the occurrence of surface peeling.

With the resolution enhancement techniques such as OPC (Optical Proximity Correction) and SRAF (Sub-Resolution Assist Features), the size of layout data have grown significantly. It is quite common now to find layout files that are tens of GBs in size. Unlike GDSII which can store data hierarchically, mask data formats such as MEBES are essentially flat and more voluminous. Moreover, polygonal data present in layout data files is fractured, thereby increasing the data volume before getting stored in MEBES data format. This results in huge MEBES files. As per the ITRS roadmap of 2005, for a 45nm half-pitch node that is expected to be in use by 2010, the mask data volume for a single layer is expected to reach up to 825 GB. Storing and transferring such large mask data are issues for which the mask industry needs solutions. Historically, MEBES is the most prevalent EB format in the industry. Moreover, in many Mask Data Preparation (MDP) flows, the MEBES format is being used as the de-facto standard for specifying the fractured EB data even though the final target EB machine might be different. In this paper we present techniques for lossless reversible compression of MEBES data, i.e., when the compressed file is decompressed, the generated uncompressed file matches the original MEBES file bit- by-bit. By applying these compression techniques a compression ratio of 5X to 15X can be obtained. In practice, compressing MEBES files is usually a one-time task, but decompression of compressed files is expected to be done multiple times as every time a compressed MEBES file needs processing, it has to be decompressed. MEBES is essentially an efficient data format and the geometries are stored compactly. As a result the compression/decompression techniques described in this paper are quite computation intensive in order to achieve higher compression ratio. This in turn leads to higher CPU time for compression/decompression compared to generic compressors such as gzip. However, as the format-specific compressors produce higher compression ratios, the disk I/O time for compression and decompression is expected to be less compared to the generic compressors such as gzip and gunzip. In spite of this, the format-specific decompressor is usually 3-5X times slower than the generic decompressor such as gunzip. Since decompression is expected to be done more frequently as compared to compression, speeding up decompression is highly desirable. We present a compression technique for MEBES data which enables multiple process threads to decompress the compressed MEBES data. With the multi-core multiprocessor machines becoming quite inexpensive and common, the multi-threaded decompression is expected to perform close to the disk I/O time on such machines. The paper details out the techniques, experimental results in terms of comparative compression ratios, compression and decompression speed using single threads and multiple threads. The possibility of getting higher compression ratios as well as higher or comparable decompression speed makes it more practical to use format specific reversible compression schemes rather than using generic compressors. Even though, the paper focuses on compression and decompression of MEBES, it can be easily extended to the compression of GDSII [1].

The popularity of general purpose Graphic Processing Unit (GPU) is largely attributed to the tremendous concurrency enabled by its underlying architecture -- single instruction multiple thread (SIMT) architecture. It keeps the context of a significant number of threads in registers to enable fast ``context switches" when the processor is stalled due to execution dependence, memory requests and etc. The SIMT architecture has a large register file evenly partitioned among all concurrent threads. Per-thread register usage determines the number of concurrent threads, which strongly affects the whole program performance. Existing register allocation techniques, extensively studied in the past several decades, are oblivious to the register contention due to the concurrent execution of many threads. They are prone to making optimization decisions that benefit single thread but degrade the whole application performance.

A period of chromosome condensation followed by decondensation occurs between premeiotic interphase and leptotene inLiliumhybrid cv. ‘Black Beauty’. The duration of this period was estimated to be about 1.16 days in pollen mother cells (p. m. cs) of plants grown at 20 °C. Preleptotene chromosome condensation and contraction also occurred in embryo sac mother cells (e. m. cs) of ‘Black Beauty’. However, the maximum degree of chromosome contraction at the preleptotene condensation stage was much greater in p. m. cs than in e. m. cs. Moreover, the preleptotene condensation and decondensation stage was apparently shorter in e. m. cs (about 0.7 days) than in p. m. cs. The developmental behaviour of p. m. c. chromosomes during pre­leptotene condensation and decondensation was essentially the same as that described by Walters (1970, 1972) for the corresponding stages inLilium longiflorumcv. ‘Croft’. A brief illustrated description is given of the appearance of p. m. cs at various stages of preleptotene chromosome condensation in both methylene blue stained anther sections, and in Feulgen stained anther squashes. ‘Black Beauty’ p. m. cs entered preleptotene chromosome condensation stage from G2 of premeiotic interphase having completed DNA synthesis. All the p. m. cs within an anther loculus underwent preleptotene chromo­some condensation stage with a degree of synchrony not less than that found at early first meiotic prophase. At maximum chromosome contration the diploid chromosome number (2n= 24) could often be counted, but no evidence of association of chromosomes was seen. At this stage the appearance of the chromosomes was indistinguishable from that of late prophase or prometaphase chromosomes at mitosis. Thereafter chromo­somes underwent decondensation and elongation and eventually passed into leptotene without first entering any other stage. The nature and possible significance of preleptotene chromosome condensation and decondensation are discussed. The appearance and behaviour of chromosomes at preleptotene condensation stage is the same as that displayed by chromosomes at mitotic prophase. Similarly, the appearance and behaviour of chromosomes at preleptotene decondensation is indistinguishable from that normally seen at mitotic telophase. It is suggested, therefore, that preleptotene condensation and decondensation represent a true mitotic reversion in which metaphase and anaphase are omitted. In normalLiliumgenotypes meiosis is initiated by p. m. cs at G2 of premeiotic interphase. In ‘Black Beauty’, however, the control regu­lating the initiation of meiosis apparently is effective later in the cell cycle and acts only after p. m. cs have entered mitotic prophase. It is concluded that preleptotene chromosome condensation stage has no effect on normal meiotic chromosome pairing behaviour and probably has no significant function. Two parallel threads (chromatids) are visible in chromosomes at preleptotene condensation stage while, in chromo­somes at leptotene, invariably only a single thread is seen. It is suggested, therefore, that chromosomes at maximum preleptotene condensation can­not enter a meiotic sequence without first undergoing a within-chromosomal reorganization of their chromatin, and that preleptotene chromo­some decondensation stage represents such a reorganization.

We propose a self-contained, flat, quadratic global placer that is simpler than existing placers and easier to integrate into timing-closure flows. It maintains lower-bound and upper-bound placements that converge to a final solution. The upper-bound placement is produced by a novel look-ahead legalization algorithm. Our placer SimPL outperforms mPL6, FastPlace3, NTUPlace3, APlace2, and Capo simultaneously in runtime and solution quality, running 7.10 times faster than mPL6 (when using a single thread) and reducing wirelength by 3% on the ISPD 2005 benchmark suite. More significant improvements are achieved on larger benchmarks. The new algorithm is amenable to parallelism, and we report empirical studies with SSE2 instructions and up to eight parallel threads.

Modern out-of-order processors have increased capacity to exploit instruction level parallelism (ILP) and memory level parallelism (MLP), e.g., by using wide superscalar pipelines and vector execution units, as well as deep buffers for inflight memory requests. These resources, however, often exhibit poor utilization rates on workloads with large working sets, e.g., in-memory databases, key-value stores, and graph analytics, as compilers and hardware struggle to expose ILP and MLP from the instruction stream automatically. In this paper, we introduce the IMLP (Instruction and Memory Level Parallelism) task programming model. IMLP tasks execute as coroutines that yield execution at annotated long-latency operations, e.g., memory accesses, divisions, or unpredictable branches. IMLP tasks are interleaved on a single thread, and integrate well with thread parallelism and vectorization. Our DSL embedded in C++, Cimple, allows exploration of task scheduling and transformations, such as buffering, vectorization, pipelining, and prefetching. We demonstrate state-of-the-art performance on core algorithms used in in-memory databases that operate on arrays, hash tables, trees, and skip lists. Cimple applications reach 2.5× throughput gains over hardware multithreading on a multi-core, and 6.4× single thread speedup.

Computational Fluid Dynamics (CFD) is an increasingly important application domain for computational scientists. In this paper, we propose and analyze optimizations necessary to run CFD simulations consisting of multi-billion-cell mesh models on large processor systems. Our investigation leverages the general industrial Navier-Stokes open-source CFD application, Code_Saturne, developed by Electricité de France (EDF). Our work considers emerging processor features such as many-core, Symmetric Multi-threading (SMT), Single Instruction Multiple Data (SIMD), Transactional Memory, and Thread Level Speculation. Initially, we have targeted per-node performance improvements by reconstructing the code and data layouts to optimally use multiple threads. We present a general loop transformation that will enable the compiler to generate OpenMP threads effectively with minimal impact to overall code structure. A renumbering scheme for mesh faces is proposed to enhance thread-level parallelism and generally improve data locality. Performance results on IBM Blue Gene/P supercomputer and Intel Xeon Westmere cluster are included.

The current demand of high network speed has led NIDS to process increasing amounts of information in less time. Consequently, most part of manufacturers have opted for hardware design implementation, which in most cases increased the price of these products. The aim of this paper focus the optimization of the performance of our NIDS APAP, based on different concurrency techniques. This upgrade increases amount of traffic per unit of time that is being processed by the system without relying on a hardware implementation. It is important to clarify that despite these measures can make our NIDS perform in real time on fast networks, it cannot achieve the same performance as a hardware implementation. As the first step it is interesting to briefly highlight some of the most important features of our initial prototype of IDS, APAP [1], with the purpose of getting into context. This system was developed as a hybrid NIDS combining signature and anomaly based detection. The system simultaneously executes Snort along with its preprocessors and an anomaly based detector whose design is based on Anagram [2]. We chose to work on CPU level parallelism using OpenMP libraries. These libraries provide an API that allows us to add concurrency to the application by means of shared memory parallelism. It is based on the creation of parallel execution threads that share variables from their parent process. OpenMP consists of a set of compiler directives, library routines, and environment variables that influence run-time behavior. The first thing to take into consideration is the degree of parallelization of the algorithm. Because the optimization could be in jeopardy if the threads context changes do not take place. Therefore, we created four testing suites corresponding to four different parallelization criteria. The first suite is a total parallelization of the algorithm, the other three are relaxations of the first by means of no parallelization of: fixed loop iterations, variable loop iterations and loops iterating to a concrete variable of the code, respectively. Notice that each suite includes the relaxations made on the previous ones. Figure 1 illustrates the time it took to run the algorithm depending on the number of threads for each level respect of the execution on a single thread. This analysis was done using a Core 2 DUO CPU processor, meaning a powerful performance may be achieved using more powerful processors. The trace used for the tests was ceded by the Computer Center of the Universidad Complutense de Madrid.

The paper presents the rationale and design of the concurrency control features of Raven, an object-oriented distributed and parallel programming language and system. Raven's parallel constructs support coarse grained parallelism and are designed to permit programmers to use parallelism with relative ease. To achieve this Raven provides automatic concurrency control on an object's instance data at method invocation time. Raven allows multiple execution threads to access an object strictly for reading or a single execution thread to access an object for the updating of instance data. Raven is operational on a variety of machine architectures, including a shared memory multiprocessor. Experience indicates Raven's concurrency support simplifies the task of converting sequential code to run in a parallel or distributed environment. >

BackgroundVarious indexing techniques have been applied by next generation sequencing read mapping tools. The choice of a particular data structure is a trade-off between memory consumption, mapping throughput, and construction time.ResultsWe present the succinct hash index – a novel data structure for read mapping which is a variant of the classical q-gram index with a particularly small memory footprint occupying between 3.5 and 5.3 GB for a human reference genome for typical parameter settings. The succinct hash index features two novel seed selection algorithms (group seeding and variable-length seeding) and an efficient parallel construction algorithm, which we have implemented to design the FEM (Fast(F) and Efficient(E) read Mapper(M)) mapper. FEM can return all read mappings within a given edit distance. Our experimental results show that FEM is scalable and outperforms other state-of-the-art all-mappers in terms of both speed and memory footprint. Compared to Masai, FEM is an order-of-magnitude faster using a single thread and two orders-of-magnitude faster when using multiple threads. Furthermore, we observe an up to 2.8-fold speedup compared to BitMapper and an order-of-magnitude speedup compared to BitMapper2 and Hobbes3.ConclusionsThe presented succinct index is the first feasible implementation of the q-gram index functionality that occupies around 3.5 GB of memory for a whole human reference genome. FEM is freely available at https://github.com/haowenz/FEM.

The work described here fits in the context of a larger project on the objective and relevant characterization of paintings and painting canvas through the analysis of multimodal digital images. We captured, amongst others, X-ray images of different canvas types, characterized by a variety of textures and weave patterns (fine and rougher texture; single thread and multiple threads per weave), including raw canvas as well as canvas processed with different primers. In this paper, we study how to characterize the canvas by extracting global features such as average thread width, average distance between successive threads (i.e. thread density) and the spatial distribution of primers. These features are then used to construct a generic model of the canvas structure. Secondly, we investigate whether we can identify different pieces of canvas coming from the same bolt. This is an important element for dating, authentication and identification of restorations. Both the global characteristics mentioned earlier and some local properties (such as deviations from the average pattern model) are used to compare the "fingerprint" of different pieces of cloth coming from the same or different bolts.

In this paper, we consider sentences that contain multiple in-text references (MIR) and their position in the rhetorical structure of articles. We carry out the analysis of MIR in a large-scale dataset of about 80,000 research articles published by the Public Library of Science in 7 journals. We analyze two major characteristics of MIR: their positions in the IMRaD structure of articles and the number of in-text references that make up a MIR in the different journals. We show that MIR are rather frequent in all sections of the rhetorical structure. In the Introduction section, sentences containing MIR account for more than half of the sentences with references. We examine the syntactic patterns that are most used in the contexts of both multiple and single in-text references and show that they are composed, for the most part, of noun groups. We point out the specificity of the Methods section in this respect.

Fuzzy Formal Concept Analysis (FFCA) is a robust mathematical tool for analyzing data, particularly where uncertainty or fuzziness is inherent. FFCA is utilized across various domains, including data mining, information retrieval, and knowledge representation. However, fuzzy concepts extraction is a crucial yet computationally intensive task. This paper addresses the challenge of time efficiency in extracting single-sided fuzzy concepts from large datasets. A parallel algorithm is proposed to reduce computational time and optimize resource utilization, thus enabling the scalable analysis of expanding datasets. By computing fuzzy concepts across multiple threads in parallel, each thread processes an attribute independently to extract fuzzy concepts, which are then merged in the final step. The proposed algorithm extracts fuzzy-crisp concepts, which are more concise than other types of fuzzy concepts. Experiments were conducted to evaluate the performance of the proposed parallel algorithm against existing sequential methods. Experimental results demonstrate significant gains in computational efficiency, with the algorithm achieving an average time reduction of 68% compared to the attribute-based algorithm and up to 83%-time reduction compared to the fuzzy CbO algorithm across various types of datasets, including binary, quantitative, and fuzzy.