SimPL: An Effective Placement Algorithm

Data parallel memory systems must maintain a large number of outstanding memory references to fully use increasing DRAM bandwidth in the presence of increasing latency. At the same time, the throughput of modern DRAMs is very sensitive to access pattern's due to the time required to precharge and activate banks and to switch between read and write access. To achieve memory reference parallelism a system may simultaneously issue references from multiple reference threads. Alternatively multiple references from a single thread can be issued in parallel. In this paper, we examine this tradeoff and show that allowing only a single thread to access DRAM at any given time significantly improves performance by increasing the locality of the reference stream and hence reducing precharge/activate operations and read/write turnaround. Simulations of scientific and multimedia applications show that generating multiple references from a single thread gives, on average, 17% better performance than generating references from two parallel threads

In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a single thread) are issued simultaneously to multiple functional units, and these instructions can begin execution unless there are functional unit conflicts. This parallel execution scheme greatly improves the utilization of the functional unit. Simulation results show that by executing two and four threads in parallel on a nine-functional-unit processor, a 2.02 and a 3.72 times speed-up, respectively, can be achieved over a conventional RISC processor.Our architecture is also applicable to the efficient execution of a single loop. In order to control functional unit conflicts between loop iterations, we have developed a new static code scheduling technique. Another loop execution scheme, by using the multiple control flow mechanism of our architecture, makes it possible to parallelize loops which are difficult to parallelize in vector or VLIW machines.

A period of chromosome condensation followed by decondensation occurs between premeiotic interphase and leptotene inLiliumhybrid cv. ‘Black Beauty’. The duration of this period was estimated to be about 1.16 days in pollen mother cells (p. m. cs) of plants grown at 20 °C. Preleptotene chromosome condensation and contraction also occurred in embryo sac mother cells (e. m. cs) of ‘Black Beauty’. However, the maximum degree of chromosome contraction at the preleptotene condensation stage was much greater in p. m. cs than in e. m. cs. Moreover, the preleptotene condensation and decondensation stage was apparently shorter in e. m. cs (about 0.7 days) than in p. m. cs. The developmental behaviour of p. m. c. chromosomes during pre­leptotene condensation and decondensation was essentially the same as that described by Walters (1970, 1972) for the corresponding stages inLilium longiflorumcv. ‘Croft’. A brief illustrated description is given of the appearance of p. m. cs at various stages of preleptotene chromosome condensation in both methylene blue stained anther sections, and in Feulgen stained anther squashes. ‘Black Beauty’ p. m. cs entered preleptotene chromosome condensation stage from G2 of premeiotic interphase having completed DNA synthesis. All the p. m. cs within an anther loculus underwent preleptotene chromo­some condensation stage with a degree of synchrony not less than that found at early first meiotic prophase. At maximum chromosome contration the diploid chromosome number (2n= 24) could often be counted, but no evidence of association of chromosomes was seen. At this stage the appearance of the chromosomes was indistinguishable from that of late prophase or prometaphase chromosomes at mitosis. Thereafter chromo­somes underwent decondensation and elongation and eventually passed into leptotene without first entering any other stage. The nature and possible significance of preleptotene chromosome condensation and decondensation are discussed. The appearance and behaviour of chromosomes at preleptotene condensation stage is the same as that displayed by chromosomes at mitotic prophase. Similarly, the appearance and behaviour of chromosomes at preleptotene decondensation is indistinguishable from that normally seen at mitotic telophase. It is suggested, therefore, that preleptotene condensation and decondensation represent a true mitotic reversion in which metaphase and anaphase are omitted. In normalLiliumgenotypes meiosis is initiated by p. m. cs at G2 of premeiotic interphase. In ‘Black Beauty’, however, the control regu­lating the initiation of meiosis apparently is effective later in the cell cycle and acts only after p. m. cs have entered mitotic prophase. It is concluded that preleptotene chromosome condensation stage has no effect on normal meiotic chromosome pairing behaviour and probably has no significant function. Two parallel threads (chromatids) are visible in chromosomes at preleptotene condensation stage while, in chromo­somes at leptotene, invariably only a single thread is seen. It is suggested, therefore, that chromosomes at maximum preleptotene condensation can­not enter a meiotic sequence without first undergoing a within-chromosomal reorganization of their chromatin, and that preleptotene chromo­some decondensation stage represents such a reorganization.

Modern out-of-order processors have increased capacity to exploit instruction level parallelism (ILP) and memory level parallelism (MLP), e.g., by using wide superscalar pipelines and vector execution units, as well as deep buffers for inflight memory requests. These resources, however, often exhibit poor utilization rates on workloads with large working sets, e.g., in-memory databases, key-value stores, and graph analytics, as compilers and hardware struggle to expose ILP and MLP from the instruction stream automatically. In this paper, we introduce the IMLP (Instruction and Memory Level Parallelism) task programming model. IMLP tasks execute as coroutines that yield execution at annotated long-latency operations, e.g., memory accesses, divisions, or unpredictable branches. IMLP tasks are interleaved on a single thread, and integrate well with thread parallelism and vectorization. Our DSL embedded in C++, Cimple, allows exploration of task scheduling and transformations, such as buffering, vectorization, pipelining, and prefetching. We demonstrate state-of-the-art performance on core algorithms used in in-memory databases that operate on arrays, hash tables, trees, and skip lists. Cimple applications reach 2.5× throughput gains over hardware multithreading on a multi-core, and 6.4× single thread speedup.

The current demand of high network speed has led NIDS to process increasing amounts of information in less time. Consequently, most part of manufacturers have opted for hardware design implementation, which in most cases increased the price of these products. The aim of this paper focus the optimization of the performance of our NIDS APAP, based on different concurrency techniques. This upgrade increases amount of traffic per unit of time that is being processed by the system without relying on a hardware implementation. It is important to clarify that despite these measures can make our NIDS perform in real time on fast networks, it cannot achieve the same performance as a hardware implementation. As the first step it is interesting to briefly highlight some of the most important features of our initial prototype of IDS, APAP [1], with the purpose of getting into context. This system was developed as a hybrid NIDS combining signature and anomaly based detection. The system simultaneously executes Snort along with its preprocessors and an anomaly based detector whose design is based on Anagram [2]. We chose to work on CPU level parallelism using OpenMP libraries. These libraries provide an API that allows us to add concurrency to the application by means of shared memory parallelism. It is based on the creation of parallel execution threads that share variables from their parent process. OpenMP consists of a set of compiler directives, library routines, and environment variables that influence run-time behavior. The first thing to take into consideration is the degree of parallelization of the algorithm. Because the optimization could be in jeopardy if the threads context changes do not take place. Therefore, we created four testing suites corresponding to four different parallelization criteria. The first suite is a total parallelization of the algorithm, the other three are relaxations of the first by means of no parallelization of: fixed loop iterations, variable loop iterations and loops iterating to a concrete variable of the code, respectively. Notice that each suite includes the relaxations made on the previous ones. Figure 1 illustrates the time it took to run the algorithm depending on the number of threads for each level respect of the execution on a single thread. This analysis was done using a Core 2 DUO CPU processor, meaning a powerful performance may be achieved using more powerful processors. The trace used for the tests was ceded by the Computer Center of the Universidad Complutense de Madrid.

In this paper, we propose a novel floor planning algorithm for GPUs. Floor planning is an inherently sequential algorithm, far from the typical programs suitable for Single Instruction Multiple Thread (SIMT) style concurrency in a GPU. We propose a fundamentally different approach of exploring the floor plan solution space, where we evaluate concurrent moves on a given floor plan. We illustrate several performance optimization techniques for this algorithm in GPUs. Compared to the sequential algorithm, our techniques achieve 4-30X speedup for a range of MCNC benchmarks, while delivering comparable or better solution quality.

Home Health Care (HHC) services are growing worldwide and, usually, the home care visits are manually planned, being a time and effort consuming task that leads to a non optimized solution. The use of some optimization techniques can significantly improve the quality of the scheduling solutions, but lacks the achievement of solutions that face the fast reaction to condition changes. In such stochastic and very volatile environments, the fast re-scheduling is crucial to maintain the system in operation. Taking advantage of the inherent distributed and intelligent characteristics of Multi-agent Systems (MAS), this paper introduces a methodology that combines the optimization features provided by centralized scheduling algorithms, e.g. genetic algorithms, with the responsiveness features provided by MAS solutions. The proposed approach was codified in Matlab and NetLogo and applied to a real-world HHC case study. The experimental results showed a significant improvement in the quality of scheduling solutions, as well as in the responsiveness to achieve those solutions.

This paper provides a novel perspective in the Protein Structure Prediction (PSP) problem. The PSP problem focuses on determining putative 3D structures of a protein starting from its primary sequence. The proposed approach relies on a multi-agents approach, where concurrent agents explore the folding of different parts of a protein. The strength of the approach lies in the agents' ability to apply different types of knowledge (expressed in the form of declarative constraints) to prune the local space of folding alternatives. The paper demonstrates the suitability of a GPU approach to implement such multi-agent infrastructure, with significant improvements in speed and quality of solutions w.r.t. other methods (e.g., based on fragments assembly approaches).

SummaryRecent work in metaheuristic algorithms has shown that solution quality may be improved by composing algorithms with orthogonal characteristics. At the same time, fused CPU‐GPU systems have emerged as a unique platform on which to study these algorithms. Using metaheuristic algorithms requires striking a balance between local and global exploration. There are no governing rules, however, to balance these. In this paper, we study two population‐based metaheuristic algorithms: multi‐swarm particle swarm optimization (MPSO) and genetic algorithms (GAs). We investigate parallel MPSO variants with genetic operators to increase quality: crossover, mutation, swapping, and all three. We develop a hybrid parallel algorithm that combines a slower convergent algorithm (GA) with a faster one (MPSO). The hybrid achieves significant initial improvement in solution quality but no significant difference in the final average fitness. Executing the GA on the GPU requires approximately an order of magnitude less time (0.07–0.18 s) than on the CPU. Our platform is the AMD A8‐3530MX accelerated processing unit that packs four ×86 CPU cores and 80 very long instruction word GPU processing elements. We make effective use of the hierarchical memory structure on the accelerated processing unit, four‐way very long instruction word vectorization, and zero‐copy buffers. Copyright © 2014 John Wiley & Sons, Ltd.

The whale optimization algorithm (WOA) is a high‐performance metaheuristic algorithm that can effectively solve many practical problems and broad application prospects. However, the original algorithm has a significant improvement in space in solving speed and precision. It is easy to fall into local optimization when facing complex or high‐dimensional problems. To solve these shortcomings, an elite strategy and spiral motion from moth flame optimization are utilized to enhance the original algorithm’s efficiency, called MEWOA. Using these two methods to build a more superior population, MEWOA further balances the exploration and exploitation phases and makes it easier for the algorithm to get rid of the local optimum. To show the proposed method’s performance, MEWOA is contrasted to other superior algorithms on a series of comprehensive benchmark functions and applied to practical engineering problems. The experimental data reveal that the MEWOA is better than the contrast algorithms in convergence speed and solution quality. Hence, it can be concluded that MEWOA has great potential in global optimization.

Evaluation of leading heuristics for the single machine tardiness problem

Planning inland vessel operations in large seaports using a two-phase approach

The development of efficient quality of service (QoS) routing algorithms in a high-speed networking or the next generation IP networking environment is a very important and at the same time very difficult task due to the need to provide divergent services with multiple QoS requirements. Recently, a heuristic algorithm H/spl I.bar/MCOP, which is based on a nonlinear Lagrange relaxation (NLR) technique, has been proposed to resolve the contradiction between the time complexity and the quality of solution. Even though H/spl I.bar/MCOP has demonstrated outstanding capability for finding feasible solutions to the multi-path constrained (MCP) problem, it has not exploited the full capability that an NLR-based technique could offer. In this paper, we propose a new NLR-based heuristic, in which the search process is interpreted from a probability perspective. Simulation results indicate that, in comparison with H/spl I.bar/MCOP, the proposed heuristic can achieve a significant performance improvement when it is used as a basic step for solving more complicated QoS routing problems.

Apache Spark is a general-purpose cluster computing system for big data processing and has drawn much attention recently from several fields, such as pattern recognition, machine learning and so on. Unlike MapReduce, Spark is especially suitable for iterative and interactive computations. With the computing power of Spark, a utility library, referred to as IRlib, is proposed in this work to accelerate large-scale image retrieval applications by jointly harnessing the power of GPU. Similar to the built-in machine learning library of Spark, namely MLlib, IRlib fits into the Spark APIs and benefits from the powerful functionalities of Spark. The main contributions of IRlib lie in two-folds. First, IRlib provides a uniform set of APIs for the programming of image retrieval applications. Second, the computational performance of Spark equipped with multiple GPUs is dramatically boosted by developing high performance modules for common image retrieval related algorithms. Comparative experiments concerning large-scale image retrieval are carried out to demonstrate the significant performance improvement achieved by IRlib as compared with single CPU thread implementation as well as Spark without GPUs employed.

A genetic algorithm for optimization of laminated dies manufacturing