Deep sub-micron chip development

The goal of this paper is to investigate design parameters of the CMOS STI diodes, intended to be used as ESD protection devices, and evaluate their performance for use in the deep submicron CMOS process. The 2-D simulations of multiple diode structures and geometries have been performed using SEQUOIA Device Designer, and the results allow to accurately predict the failure point and to optimize the different diode structures for high-speed RF applications. The proposed methodology can be used in practice to aid the design of ESD protection in deep submicron CMOS.

Capability of a deep sub-micron bulk CMOS process for low power RF applications is investigated. Very low power 5 GHz voltage-controlled oscillator and 2:1 frequency divider simulations are presented using a 0.18 /spl mu/m bulk CMOS process. The VCO uses NMOS varactors and tunes between 4.9 GHz and 6.1 GHz with a phase noise of 108.5 dBc/Hz at 1 MHz offset while drawing 490 /spl mu/A from a 1.8 V power supply. The 2:1 frequency divider is operational up to 6.7 GHz with only 100-mV peak input signal level. Divider operates with a 1-V power supply drawing only 670 /spl mu/A.

The intrinsic ESD/EOS robustness of a technology is determined by the sensitivity to thermal initiated second breakdown. We show, for the first time, high current and ESD robustness results for a deep submicron CMOS technology with drawn poly gate lengths of 0.35 /spl mu/m and oxide thicknesses down to 4.5 nm. It is shown that a transistor design window can be determined for optimized drive current and good robustness, while maintaining low off currents. An important observation is that robustness increases for smaller channel lengths and is directly proportional to the transistor drive current. Hence, robust deep submicron technologies can be designed with optimized transistor performance without using additional masks or increasing process complexity. >

First generation of deep n-well CMOS MAPS with in-pixel sparsification for the ILC vertex detector

A perimeter gated SPAD (PGSPAD), a SPAD with an additional gate terminal, prevents premature perimeter breakdown in standard CMOS SPADs. At the same time, a PGSPAD takes advantage of the benefits of standard CMOS. This includes low cost and high electronics integration capability. In this work, we simulate the effect of the applied voltage at the perimeter gate to develop a consistent electric field distribution at the junction through physical device simulation. Additionally, the effect of the shape of the device on the electric field distribution has been examined using device simulation. Simulations show circular shape devices provide a more uniform electric field distribution at the junction compared to that of rectangular and octagonal devices. We fabricated PGSPAD devices in a sub-micron process (0.5 μm CMOS process and 0.5 μm high voltage CMOS process) and a deep-submicron process (180 nm CMOS process). Experimental results show that the breakdown voltage increases with gate voltage. The breakdown voltage increases by approximately 1.5 V and 2.5 V with increasing applied gate voltage magnitude from 0 V to 6 V for devices fabricated in 0.5 μm and 180 nm standard CMOS process respectively.

The transient sensitive trigger (TST) was used to improve the RC delay time of the long interconnection in deep sub-micron process. The conventional TST circuit has a threshold voltage drop during transitions which results in a longer delay time. In this work, modified techniques are proposed to improve the drawbacks of the conventional TST. The new versions have 45-74% delay improvement compared to the conventional TST, simulated using a 0.25 /spl mu/m CMOS process. The proposed circuits can be applied to the receiving of long interconnection signals for high-speed VLSI applications.

In the search for new physics, the Large Hadron Collider at CERN will be upgraded around year 2025, increasing its integrated luminosity by an order of magnitude. For the Inner Tracker (ITk) of the ATLAS experiment, the elevated levels of radiation, pile-up and data rate will require a complete replacement. Active pixel sensors built in sub-micron High Voltage CMOS (HV-CMOS) processes are candidates for the ITk outer pixel detector layers. Being high voltage tolerant, thus supporting drift-based charge collection, they allow to build radiation hard detectors in industry standard technology. On-sensor signal processing permits replacing complex and cost-intensive hybridisation techniques by simpler ones, ultimately leading to fully monolithic devices. In this thesis, sensors built in the ams H18 180nm process were investigated as hybrid detectors. Several design versions were characterised in laboratory and in-beam measurements. The FE-I4 Telescope, a particle tracker for beam based detector characterisation was built to facilitate measurements on HV-CMOS sensors. Its construction and performance as well as the findings on detection performance of the HV-CMOS prototypes, especially after irradiation, are presented.

Digitisation of signals at RF imposes severe noise and linearity constraints. Furthermore, the drive towards integration with deep submicron CMOS process aggravates the difficulties in high frequency mixed signal circuit design. This paper first summarises the challenges in system and circuit facing GHz IF complex sampling. It then proposes a charge sampling receiver architecture which combines MEMS filter and complex FIR sampling filter in order to achieve high IF digitization suitable for multi-standard cellular applications. The architecture is validated through system behavioural models emulating deep submicron MOS characteristics. It can be shown that with existing MEMS filter technology and advanced standard CMOS process, it is possible to realise a reconfigurable high IF SDR receiver. A circuit version of integrated MEMS filter and sampling filter in CMOS is in the works to validate the proposed system.

In this paper, the design and applications of high-speed interconnect transceivers are presented. Serial interconnect transceivers have been widely adopted for its high data transfer rate, low cost, good noise immunity and low EMI. Signal SNR can be severely degraded by transmission channel. Channel modeling and analysis are very critical in high-speed serial transceiver design. Effects due to channel impairments and tradeoffs among different equalization techniques are discussed in the paper. Implementation examples of key building blocks for high-speed serial transceiver in deep sub-micron CMOS logic process are also introduced.

A Time to Digital Converter VLSI chip for high-energy physics experiment is developed. A low-power and high-density characteristics of the chip are attained by using submicron CMOS process and a new circuit technique which use memory cells and gate delay. In order to achieve excellent stability of time measurement, an internal feed-back circuit is also introduced.

Contrast Enhancement Lithography has been in existence for almost two decades, yet its practical advantages are relatively unknown among the general lithography community. This paper attempts to redress this situation by discussing the implementation of a Contrast Enhancement Material into manufacturing. Contrast Enhancement Materials (CEMs) are photobleachable solutions applied as a thin top coat to the photoresist after softbake. The CEM is initially opaque at the actinic wavelength but becomes essentially transparent upon exposure. Optimising the relative bleaching parameters of the photoresist and the Contrast Enhancement Material makes it possible to prevent exposure in nominally unexposed resist regions, while bleaching the exposed resist areas. Thus, a temporary contact mask is formed on the photoresist during exposure, allowing high-intensity parts of the aerial image to pass through while eliminating low intensity regions. The resulting aerial image which exposes the photoresist has higher contrast than the original. This allows superior resist depth-of-focus, improves resist profile, increases exposure latitudes and reduces proximity effects among other benefits. Initially, this paper discusses the chemistry and physics of the CEM process. Next the authors look at the lithographic requirements for a final metal level on a sub-micron CMOS process. Analysis of the Depth-Of-Focus error budget indicated that the process would not be manufacturable without significantly increased DOF. The authors also present the results of the characterization of the CEM, including simulation work, with regard to the effect on primary lithography outputs such as depth-of-focus, resist sidewall and exposure latitude.

In sub-micron CMOS processes, it has become increasingly difficult to identify and separate outliers from the intrinsic distribution at test. This is due to the increasing inadequacy of reliability screens such as burn-in and IDDQ testing. Statistical Post-Processing (SPP) methods have been developed to run off-tester using the raw data generated from Automatic Test Equipment (ATE) and wafersort maps. Post-Processing modules include advanced IDDQ tests such as Delta IDDQ and the Nearest Neighbor Residual (NNR), as well as other non-IDDQ based reliability-focused modules. This work presents the application and results of SPP at LSI Logic on 0.18 /spl mu/m CMOS products. Challenges of production implementation have been overcome, which include user definable adaptive threshold limits, handling multiple data sources, and data flow management. Burn-in data and customer Defects per Million units (DPM) data show a 30-60% decrease in failure rate with SPP implementation with very acceptable yield loss.

A self‐aligned silicidation scheme for a submicron complementary metal oxide semiconductor process with three different types of poly‐Si gate doping is discussed. High temperature (730°C) rapid thermal processing of a Ti layer capped with was found to yield the stable C54 material phase. formed on moderately doped mono‐ and poly‐Si can withstand aggressive environments of low pressure chemical vapor deposited tetraethylorthosilicate deposition, while the films formed on more heavily doped substrates were found to require additional stabilization at higher temperatures.

Monolithic system integration of optical components, photodetectors, and analog transimpedance CMOS amplifiers is presented. An advanced SWAMI LOCOS technique, based on a submicron CMOS process is applied. Different optical devices including waveguides, beam splitters, interferometers and mirrors have been integrated using this technique. The optical system consists of a SiON layer deposited on 2-/spl mu/m oxide. The waveguides are made of structured SiO/sub 2/ layers on top of the SiON layer. Leaky wave or butt coupled photodiodes and phototransistors are used as light detectors. The photocurrents are amplified by low-noise CMOS transimpedance amplifiers with high sensitivity. They were designed for a large dynamic range of photocurrents together with short recovery times and low noise. Their reliability and yield were optimized with new CAD tools.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Leakage power has become an important contributing factor of power for the CMOS circuits in deep sub-micron process.MTCMOS is a very effective technique to reduce the leakage current of circuits in the standby mode.Placing a global sleep device is not practical and sleep device at fine grain level involves more number of sleep transistors and more routing space.Distributed MTCMOS is better technique with self sleep circuit to avoid complexities in routing and sleep distribution network.A simple FFT processor is designed with self sleep buffer using body bias to reduce its standby power.Ccomparisons are made between leakage power for FFT implemented in CMOS and distributed self sleep FFT using the 90nm CMOS technology in cadence tools.