Design of Low Power FFT using Self-sleep Buffer with Body bias Technique

Temperature effect inversion (TEI) phenomenon in ultralow power (ULP) very large scale integration circuits has been identified as an important effect by both academia and industry. Although a number of ULP methods that attempt to exploit the TEI phenomenon have been proposed, the small size of the design exploration space when applying these methods to ULP circuits hinders them from achieving their full potential. This is mainly due to the limited granularity of the supply voltage level control. Starting with an intuition that the body biasing (BB) technique is a key to overcome this limitation, this paper exploits the BB technique along with the TEI-aware voltage scaling (TEI-VS) method and TEI-aware frequency scaling (TEI-FS) method, so as to substantially increase the design spaces of these methods. Techniques for optimally combining the BB technique with TEI-VS and TEI-FS are introduced. Simulation results with the latest commercial CMOS process technologies for ULP designs demonstrate the effectiveness of the proposed methodology.

As fabrication technology progresses, several new challenges follow. Among them, the most noticeable two are process variations and leakage current of the circuit. To tackle these two problems, an effective way is to use body biasing technique. In substance, using RBB technique can minimize leakage current but increase the delay of a gate. FBB technique decreases the delay but increases leakage current. In previous works, a single body biasing is applied to whole circuit. In a slow circuit, since the FBB is applied to whole circuit, the leakage current increases dramatically. In a fast circuit, RBB is applied to decrease the leakage current. However, without violating the timing specification, the value of body biasing is restricted by the critical paths, and the saving of leakage current is limited. In this paper, we propose a design flow to partition the circuit into subcircuits so that each subcircuit can be applied its individual RBB or FBB to reduce the leakage current and cope with process variations. In the experimental result, our method is able to save leakage current from 41% to 46% as compared with design without body biasing technique. Under process variations, our method can save 40% to 49% leakage on fast circuits and 15% to 32% on slow circuits.

In the IoT for multi-sensor node application [1], there are demanded both high-performance for computation in an active mode, and an ultra-low standby power in a sleep mode for longtime buttery life in the energy efficient system. Ultra-low standby MCU with embedded NVM using 90 nm CMOS technology is also reported [2], but its SRAM cache is not sufficient for applying imaging processing which requires large memory capacity with imaging sensors in edge computing. Embedded SRAMs can be achieved fast read/write access within a few nanoseconds, but consume standby leakage power for data retention, being dominant power in the sleep mode. To reduce the standby leakage power of embedded SRAMs, the source bias design technique with power-gating is introduced on a bulk CMOS device [3]. In the resume standby (RS) mode, the VSS source bias control for SRAM array is demonstrated as an effective SRAM leakage power reduction. Besides, once the large SRAM array are into the resume standby mode, it takes long time to wake-up again. It is not applicable for high-speed CPU operation. Then, a fast resume standby mode (FRS) for cache memories is proposed to wake-up as much as fast. In that FRS mode, the power supply for SRAM peripheral is cutoff but SRAM array is keeping with a VDD supply. Each standby mode and its circuit diagram are summarized in Fig. 1. Meanwhile, dopant-less channel fully-depleted (FD) silicon-on-insulator (SOI) device is proposed [4]–[6] to improve the performance, power, and area (PPA) of embedded SRAMs. FD-SOI enables to control the back-bias (BB) dynamically under the buried-oxide (BOX) to reduce leakage current and/or to improve performance by applying reverse or forward bias, respectively. Fig. 2 presents the block diagram of BB control scheme for voltage scaling in IoT application with FD-SOI structure [7]–[9]. BBs for NMOS (VBN) and PMOS (VBP) can be applied individually by VBB generator (VBB Gen.) circuit. Four operation modes for smart IoT applications are considered. High-performance, normal, low-power operating modes are introduced, along with the required loads in the system. The sleep mode with SRAM data retention for long-term waiting in the sensor nodes is also proposed. Each supply voltage and BB is also shown in Fig. 2. The comparison of embedded SRAM leakage power is shown in Fig. 3.

The demands of future computing have led to challenges of very deep submicron (DSM) regime. As a result, leakage power dissipation is rapidly becoming a substantial contributor to the total power dissipation as threshold voltage becomes small, according to the International Technology Roadmap for Semiconductors (ITRS). In this paper a new low leakage power technique, named “MTSCStack” has been proposed. The proposed method is based on reducing leakage power in active mode and standby mode while saving exact logic state during sleep mode. Library designed using 65 nm BSIM 4 model of Berkeley Predictive Technology Model (BPTM) has been used to simulate proposed technique.

This paper presents sub-1V, low voltage and low power reference voltage using a body biasing technique. The body biasing is used to generate a supply independent current as well as the output reference voltage. The gate to source voltage difference is used to obtain the output voltage. The proposed reference voltage is implemented and simulated in Cadence Virtuoso using SCL180nm CMOS technology model for 0.55-1.8V supply range. The average output reference voltage of 250mV is obtained at room temperature with the line regulation of 1.9mV/V. The supply current of 40nA is found at 0.55V supply along with minimum temperature coefficient (TC) of 28.6ppm/oC for a temperature range of -50 to 90oC. A high-value PSRR of - 44dB at 100Hz and -16dB at 1MHz is achieved. It has an area of 0.0036mm2.

Recent trends in CMOS technology and scaling of devices clearly indicate that leakage power in digital circuits would be crucial and largely depend on the sub-threshold currents. Minimizing leakage, by power gating logic circuits using sleep transistors gives considerable power savings. However, this technique cannot be used in sequential circuits and memory cells, as it would result in loss of stored data. In this paper, we propose a novel circuit by applying a self-bias transistor (SBT) to minimize sub-threshold leakage currents in static and dynamic circuits. This circuit with SBTs, acts as a smart switch by virtually power gating either pull-up or pull-down logic, and causes a considerable reduction in leakage currents in both active and standby modes. A benchmark is simulated with 0.18 /spl mu/m CMOS technology in the Cadence Spectre circuit simulator. Results show significant reduction in leakage power, of up to 50% on average, for all possible states simulated in static and dynamic circuits by applying this proposed self-bias transistor.

Carbon Nanotube Field Effect Transistor (CNFET) has emerged as an alternative material to silicon for high performance, high stability and low power Static Random Access Memory (SRAM) design in recent years. SRAM functions as cache memory in computers and many portable devices. Therefore, CNFET based SRAM cell design is desired for low standby power cache memory. In CNFET based six transistor SRAM cell, access transistors contribute significantly to the leakage power during standby mode. This paper proposes a technique to reduce the standby power of SRAM by scaling the channel length of access transistor. An optimum channel length is selected using HSPICE simulation to ensure best performance in terms of stability, standby power and write time. The proposed design results in 37.2% and 40.6% improvements in standby power and static noise margin (SNM) respectively compared to the conventional CNFET SRAM cell with minimal write time trade off.

There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits remain in stand-by (or sleep) mode significantly longer than in active mode, their stand-by current, and not their active switching current, determines their battery life. Hence, stringent specifications are being placed on the stand-by (or leakage) current drawn by such devices. As the power supply voltage is reduced, the threshold voltage of transistors is scaled down to maintain a constant switching speed. Since reducing the threshold voltage increases the leakage of a device exponentially, leakage current has become a dominant factor in the design of VLSI circuits. In this paper, we describe a method that uses simultaneous dynamic voltage scaling (DVS) and adaptive body biasing (ABB) to reduce the total power consumption of a processor under dynamic computational workloads. Analytical models of the leakage current, dynamic power, and frequency as a function of supply voltage and body bias are derived and verified with SPICE simulation. Given these models, we show how to derive an analytical expression for the optimal trade-off between supply voltage and body bias, given a required clock frequency and duration of operation. The proposed method is then applied to a processor and is compared with DVS alone for workloads obtained using real-time monitoring of processor utilization for four typical applications.

In deep sub-100nm technologies, the exponential increase of static leakage current pose serious design challenges as we try to build efficient low power systems with faster memory cores. Consequently, it is imperative to design systems that adopt leakage control techniques during both standby and active mode. In the recent past, the size of memory cores also has been increasing at a very rapid pace to cope with the demands of high computing processors. Such large memory cores will lead to significant leakage power dissipation, as most of the devices will be in a dormant or standby mode. This study addresses the static current dissipation problem in an SRAM memory core, by implementing a combinatorial approach to reduce leakage current. In this approach we have combined multiple-Vth devices, high-oxide thickness devices and dynamic Vth techniques to reduce both subthreshold and gate-oxide leakage current. There is a ~60% savings in the total static current dissipated as compared to a conventional SRAM cell

In the past days, many consumers could simply unplug their appliances and go on holidays, assuming that their electricity meter would just stop. Standby power is a power consumed by an appliance when switched off or not performing its primary functions. Standby power consumption provides good oppourtunity for reducing both energy consumption and green house gas emissions. Through co-operation among governments, industry and consumers and the co-ordination of international policies, standby modes can be made more efficient, thereby reducing the overall demand for power . In this paper, standby power consumption of various domestic appliances was determined using an energy cost meter. The experimental results shows that the standby power of various house hold electrical appliances is consuming more electricity during standby mode.

As the world is currently heading towards an era of prolonged battery life which has forced the chip designers to go for the scaling down of the supply voltage i.e. to operate in the sub threshold region for the reduced power supply consumption, thereby causing the performance deterioration of the circuit in terms of the noise immunity. So, comes the need of such a circuit which can be used as a provision for improving the noise immunity of the circuit, thereby resulting in the development of the Schmitt trigger. This paper presents the circuit design of low voltage high speed Schmitt trigger with the feature of adjustable hysteresis, which is implemented using the body biasing technique and a comparison of the results in terms of the propagation delay is presented with respect to the conventional Schmitt trigger circuit in 180nm CMOS technology using Cadence Virtuoso. Also, the effect of the body biasing voltage for controlling the width of the hysteresis-loop is shown thereby suggesting the appropriate voltage of the body terminal of CMOS transistors based upon the fact that greater the width of the hysteresis loop greater will be the immunity of the circuit.

In the full adder, various technologies is applied to reduce leakage power. These technologies are Input vector, Stacking Technique, Power gating technique but here, leakage power has been reduced in full adder with Sub-threshold Technique. Sub-threshold technique is applied over the N-MOS and P-MOS of full adder and around 60% of power is reduced in full design. We have observed for the leakage power, noise margin and delay variations by using this approach and other technologies has compared with the proposed sub-threshold technique. This technique is best of all previous technique in which the leakage power and total power is taken and sub-threshold is applied over it. The Cadence tool (180nm) is used there.

This paper presents a new method to reduce the standby leakage power consumption using the body bias and pin reordering technique for nanometer-scale CMOS circuits. The proposed method, unlike the conventional reverse body biasing (RBB) technique, considers gate leakage to minimize the negative effects of the existing RBB approach. This minimization of the negative effects can be achieved by intelligently applying proper body bias to the appropriate CMOS network based on its status (on-/off-state) with the aid of a pin reordering technique. Experimental results on ISCAS’85 benchmark circuits show that the proposed method can achieve improvements in terms of leakage power savings that range from 16% to 38% when compared with the previous works.

Stability and performance of conventional SRAM cells operating at low voltages are severely affected due to enhanced process variations. This paper proposes a Transmission Gate (TG) based 9T SRAM cell with independent read/write operation and compares its performance with 6T, 8T, and 10T SRAM cells. The enhanced read and write ability of the cell is due to the selective use of positive feedback loop. To show the efficacy of the proposed technique, simulations are carried out using 130nm UMC technology files on Cadence Virtuoso and HSPICE. The transistor size with minimum length and width is used in each configuration using the UMC 130nm technology file for all the simulations. Various body biasing techniques (Reverse Body Bias and Forward Body Bias) are applied to reduce active and standby power. It has been observed that the proposed cell shows better results in terms of enhanced read, write and hold stability and for reduced power also. Further, the write access time is less for the proposed cell. The layout of the proposed architecture is also shown.

Transistor aging is a major reliability concern for nanoscale CMOS technology that can significantly reduce the operation lifetime of very large-scale integration chips. Negative bias temperature instability (NBTI) is a major contributor to transistor aging that affects pMOS transistors. On the other hand, leakage power is becoming a dominant factor of the total power with successive technology scaling. Since the input combinations applied to a logic core have a significant impact on both NBTI and leakage power, input vector control can be used to optimize both phenomena during idle cycles. In this paper, we present an efficient input vector selection technique based on linear programming for cooptimizing the NBTI-induced delay degradation and leakage power consumption during standby mode. Since the NBTI-induced delay degradation and leakage power are not affected by the input vector in the same direction, we provide a pareto curve based on both phenomena. A suitable point from such a pareto curve is chosen based on circuit conditions and requirements during runtime.