High-speed receivers for on-chip interconnections in deep-submicron process

Deep sub-micron chip development

A perimeter gated SPAD (PGSPAD), a SPAD with an additional gate terminal, prevents premature perimeter breakdown in standard CMOS SPADs. At the same time, a PGSPAD takes advantage of the benefits of standard CMOS. This includes low cost and high electronics integration capability. In this work, we simulate the effect of the applied voltage at the perimeter gate to develop a consistent electric field distribution at the junction through physical device simulation. Additionally, the effect of the shape of the device on the electric field distribution has been examined using device simulation. Simulations show circular shape devices provide a more uniform electric field distribution at the junction compared to that of rectangular and octagonal devices. We fabricated PGSPAD devices in a sub-micron process (0.5 μm CMOS process and 0.5 μm high voltage CMOS process) and a deep-submicron process (180 nm CMOS process). Experimental results show that the breakdown voltage increases with gate voltage. The breakdown voltage increases by approximately 1.5 V and 2.5 V with increasing applied gate voltage magnitude from 0 V to 6 V for devices fabricated in 0.5 μm and 180 nm standard CMOS process respectively.

Relative hydraulic resistance, shear rate, and pressure in a vascular network integrate the network's architecture via fluid flow, and determine vein dynamics, with a time delay, in the prototypical organism Physarum polycephalum.

Due to the development of high performance portable applications associated to the high-density integration allowed by deep submicron processes, circuit optimization under delay constraints has emerged as a critical issue for VLSI designers. The objective of this work is to avoid the use of random mathematical methods (very CPU time expensive), by defining simple, fast and deterministic indicators allowing easy and fast implementation of circuits at the required speed. We propose to extend the method of equal sensitivity, previously developed for combinatorial paths [1], to circuit sizing in order to solve the circuit convergence branch problem. We propose a coefficient based approach to solve the divergence branch problem. Validation is given by comparing with an industrial tool the performance of different benchmarks implemented in a standard 180nm CMOS process.

The ring oscillator (RO) is applied to many modern circuits given its simplicity, low-area-cost, low-power. However, the temperature-drifting propagation delay of logic gates makes the RO a difficult solution for frequency reference design in deep submicron process. This work presents the design and implementation of a temperature self-compensation architecture based on a balanced hybrid ring oscillator (BHRO) for precise temperature compensation and clock-on-chip applications. The proposed BHRO is formed by both PTAT (proportional to the absolute temperature) and CTAT (complementary to absolute temperature) delay cells to implements RO-internal compensation. The features include temperature-self-compensation, process insensitive and low-area-cost. Four different test chips are fabricated in the 0.13μm CMOS process. The measurement result exhibits two performance-friendly BHRO architectures with a best temperature coefficient of 31 ppm/C over -55 to 80 , which is among the lowest to our best knowledge. The output compensated frequency is verified to be adjustable varying from 6.95 MHz to 26.5MHz, which are the highest as we have known.

In the laboratory, partially water-wet systems are often mistaken for completely oil-wet systems, because imbibition only starts after removal of the oil layer, which originally covers the grains. The (long) time required to remove the oil film will be referred to as delay time. Incorporation of delay time in a more general description of capillary pressure and relative permeability functions is called the non-equilibrium effect. No attempt has yet been made to model non-equilibrium effects in fractured reservoirs for a field-scale problem and this is the main innovative aspect of this paper. We apply homogenization to derive an upscaled model for fractured reservoirs and include delay time effects. Furthermore, we develop a computationally efficient numerical approach to solve the upscaled model. The upscaled model overcomes limitations of the dual-porosity model including the use of a transfer function and shape factor. This paper examines various aspects of wettability behavior in fractured reservoirs, viz., the contact angle, mixed wetting, and non-equilibrium effects in capillary pressure. The main characteristic that determines reservoir behavior is the Peclet number that expresses the ratio of the average imbibition time divided by the residence time of the fluids in the fractures.At low Peclet numbers and thus high gravity numbers, under-riding is aggravated by large contact angles and longer delay times. However, for low Peclet and low gravity numbers, the effect of contact angle and delay time for the non-equilibrium effects can be ignored without appreciable loss of accuracy. For low Peclet numbers, the recovery for the mixed-wet fracture/mixed-wet matrix case is more than for the water-wet fracture/mixed-wet matrix case because a combination of capillary imbibition and gravity drainage occurs in the former case. For low Peclet numbers, the ultimate oil recovery for the water-wet fracture/mixed-wet matrix case is about the matrix Amott index times the recovery obtained for completely water-wet reservoirs. For residence times of water in the fractured reservoir much longer than the delay time, the delay time (non-equilibrium effect) does not influence the oil recovery qualitatively. Conversely, for high Peclet numbers, the residence time of water in the fractures is short and the relatively longer delay times reduce the cumulative oil production considerably as expected. Furthermore, at high Peclet numbers, after water breakthrough, the oil recovery appears to be approximately proportional to the cosine of the contact angle. It is important to distinguish between truly oil-wet systems and systems that are water-wet with long delay times. The efficiency of waterflooding in naturally fractured oil reservoirs decreases in the sequence of completely water-wet, mixed-wet fracture/mixed-wet matrix, water-wet fracture/mixed-wet matrix, and completely oil-wet, respectively. For the same amount of injected water, the recovery at low Peclet numbers is larger than the recovery at high Peclet numbers.

The Elmore base delay calculation method has long been in use, but this method cannot meet accuracy demands of current designs using deep sub-micron processes. On the other hand, SPICE can provide high accuracy, but it is very time consuming. Therefore, a novel, highly accurate and high-speed delay analysis method is proposed: MOR (model order reduction). We applied it in interconnect signal analysis to evaluate its performance

TCAD has contributed to processldevice design and prediction of the device performances for decades. This role is still very important in very deep submicron process; however, new aspect in the semiconductor industry has arisen. Interconnect issue becomes more critical in SoC timing closure. ITRS roadmap predicts future of processldevices and interconnects, which lead to a standardized process and device. TCAD seems to be requested to contribute in the new situation of SoC era. The panel addresses topics such as: What is the new role of TCAD in SoC era? How TCAD can contribute towards the ultimate-solution in timing closure problem. How to attack SI(Signa1 Integrity) Physical Design by TCAD. Can TCAD make innovation on Process & Device, which changes the ITRS2001?

Digital single event transients induced in combinatorial logic are quickly becoming a significant error source as circuit feature sizes shrink and digital circuits operate faster. In this paper, we are able to compare the combinatorial logic error rate to the sequential logic error rate in both heavy ion and proton environments in a simple digital circuit created in a 0.18 /spl mu/m CMOS technology. We are able to do this by comparing data from two unique test chips.

This paper covers the design flow and CAD tools needed to design a modern microprocessor. It reviews the existing tools for the logical and physical design of microprocessors, and then focuses on the changes and extensions to those tools needed to cope with deep submicron processes.

Leakage power has become an important contributing factor of power for the CMOS circuits in deep sub-micron process.MTCMOS is a very effective technique to reduce the leakage current of circuits in the standby mode.Placing a global sleep device is not practical and sleep device at fine grain level involves more number of sleep transistors and more routing space.Distributed MTCMOS is better technique with self sleep circuit to avoid complexities in routing and sleep distribution network.A simple FFT processor is designed with self sleep buffer using body bias to reduce its standby power.Ccomparisons are made between leakage power for FFT implemented in CMOS and distributed self sleep FFT using the 90nm CMOS technology in cadence tools.

Device failure mechanisms of today's deep sub-micron processes are not well-modeled by single stuck-at faults, and hence several advanced fault models have been proposed in the past. Gate-exhaustive fault models were proposed to exercise a gate completely and then observe the resultant response at an observable output. This paper extends the gate-exhaustive fault model to target bigger regions (a collection of gates) with the hypothesis that exercising a region with an exhaustive pattern set can yield coverage on a larger proportion of unmodeled defects. To test out this hypothesis, we use the logic proximity bridge (LPB) fault model as a surrogate for unmodeled defects and grade the region and gate exhaustive patterns against the LPB fault model to gauge their efficacy. We show that region exhaustive patterns are better at detecting untargeted LPB faults compared to patterns obtained using gate exhaustive or traditional stuck-at fault models.

Recently, energy dissipation in microprocessors is getting larger, which leads to a serious problem in terms of allowable temperature and performance improvement for future microprocessors. Cache memory is effective in bridging a growing speed gap between a processor and relatively slow external main memory, and has increased in its size. However, energy dissipation in the cache memory will approach or exceed 50% of the increasing total energy dissipation in processors. An important point to note is that, in the near future, static (leakage) energy will dominate the total energy consumption in deep sub-micron processes. This paper describes a code-generation technique that utilizes special instructions for energy reduction. The instructions perform self-invalidation in cache memories, which leads to efficient energy reduction. We developed a source-to-source-code compiler that implements the automatic code-generation. The simulation results of the generated codes show that our techniques can reduce a substantial amount of leakage energy without large performance degradation.

Leakage current is the main source of power dissipation in low-frequency digital circuits implemented in deep submicron processes. This contribution introduces a novel active-mode leakage reduction technique for ultra-low-power (ULP) low-frequency applications. It is based on the ULP CMOS logic style achieving negative-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> self-biasing ULP logic gates have static current reduced by several orders of magnitude. For a commercial 0.13-μm technology, power consumption of ULP gates at low frequencies is lower than standard CMOS counterparts even considering high-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> devices, subthreshold operation and reverse body biasing. ULP gates are shown to be very stable against process, voltage and temperature variations.

Inductor current information can be used by digitally controlled DC-DC converters as control signal or over-current protection. In most of the existing approaches, the digital inductor current-sensing and quantization are always designed and implemented as two separated functional blocks, e.g. an analog current sensor and an ADC. This is actually a redundant approach and designing a high-gain amplifier in deep sub-micron process is power consuming. Therefore, this paper proposed an on-chip digital inductor current sensor which combines both the sensing and quantization into a single functional block. In this way, chip area and power consumption can be saved. An 8-bit digital inductor current sensor for 4MHz buck converter is designed and implemented. Simulation results show that the sensor has linear and monotonic properties with LSB of 2.7mA.