Automatic Application of Last-Touch Instructions for Leakage Energy Reduction

Summary form only given. An approach towards an information theoretic based analysis and design of cache memories is presented. Computer systems usually have a slow main memory and a faster cache memory, usually much smaller than the main memory because of its cost. A somewhat similar situation is present also in Internet servers. A miss happens whenever an item is not found in the cache memory. If so, the item is fetched from the main memory and placed in the cache. A hit is obtained whenever the item is found in the cache. Usually the cost of a miss is several times that of a hit. The goal is to find strategies for the many to one mapping of addresses of the main memory to the cache memory, as well as the replacement strategies. Usual replacement strategies are least recently used, LRU, random replacement, RR, etc. The main goal is to obtain strategies that will optimize the running time of the program under execution. Since almost all programs use branch instructions and loops, some of the information theoretic approaches previously introduced consider the prediction of the result of a branch based on its past behavior. Here a different approach is considered. In particular the opposite case is analysed, i.e. a linear loop that is executed indefinitely. In particular a combined random replacement and least recently used strategy is analyzed. It is shown that this model is equivalent to the one of classifying N objects in M classes with at least c objects in each class, and that this problem gives a generalization of the Ehrenfests' urn model used in statistical thermodynamics in connection with the Boltzmann H-theorem.

Static energy consumption due to subthreshold leakage current is an overriding problem in SRAM structures such as on chip cache memories. To overcome this challenge, several techniques limiting the subthreshold current in a SRAM cell have been proposed. They limit the subthreshold current in a SRAM cell but they also cause an increase in dynamic energy during the cell access operation. In this paper the actual energy saving offered by these techniques in the context of a microprocessor memory hierarchy consisting of two cache levels is examined. A new SRAM scheme is also proposed which does not introduce time and energy penalties with respect to the conventional 6T cell. Simulations based on UMC 0.18mum-1.8V and ST 90nm-1V process models demonstrate that the conventional low-leakage techniques save a significant amount of leakage energy but they also increase the dynamic energy dissipation and the access delay. By using the technique proposed here the static energy dissipation is reduced up to 42% with respect to the 6T cell without increasing the dynamic energy dissipation or the cell access delay

Leakage energy has become an increasingly large fraction of total energy consumption, making it important to reduce leakage energy for improving the overall energy efficiency for embedded processors. In this paper, we explore how to reduce the cache leakage energy efficiently in a hybrid Scratch-Pad Memory (SPM) and cache architecture. Different from stand-alone cache, since the frequently used data may be allocated to the SPM for rapid retrieval in the hybrid architecture, the access frequency to the cache is reduced. It is possible to place the cache lines of the hybrid SPM-cache into the low power mode more aggressively than traditional leakage management for regular caches, which can reduce more leakage energy without significant performance degradation. Also, we propose a Hybrid Drowsy-Gated VDD (HDG) technique, which can adaptively exploit both short and long idle intervals of cache accesses to minimize leakage energy with insignificant performance overhead. In addition, we discussed the impact of cache size on the idle intervals of accesses, which will affect the efficiency of leakage management methods that exploit the idle intervals to reduce leakage energy.

In the realm of modern computing, cache memory serves as an essential intermediary, mitigating the speed disparity between rapid processors and slower main memory. Central to this study is the development of an innovative cache controller for a 4-way set associative cache, meticulously crafted using VHDL and structured as a Finite State Machine. This controller efficiently oversees a cache of 256 bytes, with each block encompassing 128 bits or 16 bytes, organized into four sets containing four lines each. A key feature of this design is the incorporation of the Tree Pseudo Least Recently Used (PLRU) algorithm for cache replacement, a strategic choice aimed at optimizing cache performance. The effectiveness of this controller was rigorously evaluated using ModelSim, which generated a comprehensive timing diagram to validate the design's functionality, especially when integrated with a segmented main memory of four 1KB banks. The results from this evaluation were promising, showcasing precise logic outputs within the timing diagram. Operational efficiency was evidenced by the controller's swift processing speeds: read hits were completed in a mere three cycles, read misses in five and a half cycles, and both write hits and misses in three and a half cycles. These findings highlight the controller's capability to enhance cache memory efficiency, striking a balance between the complexities of set-associative mapping and the need for optimized performance in contemporary computing systems. This study not only demonstrates the potential of the proposed cache controller design in bridging the processor-memory speed gap but also contributes significantly to the field of cache memory management by offering a viable solution to the challenges posed by traditional cache configurations.

General-purpose graphics processing units (GPGPUs) usually employ a huge register file (RF) to support massive multithreading, which however, is also responsible for a large fraction of GPGPU's total power. In this paper, we propose three RF drowsy policies and evaluate their effectiveness on leakage energy reduction. In the first drowsy policy called immediate sleep (Drowsy-IS), registers keep staying in the drowsy mode unless they are accessed, which are then put into the drowsy mode again immediately to minimize the leakage energy consumption. The second policy named temporary awake (Drowsy-TA) holds the registers in the normal (i.e. active) mode for a certain period after being accessed to wait for the next access. The registers are placed into the drowsy mode until that period expires without any access activity. Finally, we propose an adaptive policy named Drowsy-RI which identifies the re-access interval for each register at run-time and lets registers wait for the predicted intervals before putting them into the drowsy mode. The experimental results show that compared to the baseline RF, Drowsy-IS achieves 91.7% RF leakage energy reduction on average at the cost of 4.4% performance degradation. Drowsy-TA leads to negligible performance overhead, and 82.8% leakage energy reduction. By balancing the energy saving and the performance overhead, Drowsy-RI saves more RF leakage energy (87.3%) than Drowsy-TA and achieves less performance degradation (2.7%) than Drowsy-IS.

In current computer memory system hierarchy, registers and cache are both used to bridge the reference delay gap between the fast processor(s) and the slow main memory. While registers are managed by the compiler using program flow analysis, cache is mainly controlled by hardware without any program understanding. Due to the lack of coordination in managing these two memory structures, significant loss of system performance results because:

In this paper, we present a novel HitME (Hit-MEmory) buffer to reduce the energy consumption of memory hierarchy in embedded processors. The HitME buffer is a small direct-mapped cache memory that is added as additional memory into existing cache memory hierarchies. The HitME buffer is loaded only when there is a hit on L1 cache. Otherwise, L1 cache is updated from the memory and the processor's memory request is served directly from the L1 cache. The strategy works due to the fact that 90% of memory accesses are only accessed once, and these often pollute the cache. Energy reduction is achieved by reducing the number of accesses to the L1 cache memory. Experimental results show that the use of HitME buffer will reduce the L1 cache accesses resulting in a reduction in the energy consumption of the memory hierarchy. This decrease in L1 cache accesses reduces the cache system energy consumption by an average of 60.9% when compared to traditional L1 cache memory architecture and an energy reduction of 6.4% when compared to filter cache architecture for 70nm cache technology.

Innovative architectural design may be the best route to create an economical and efficient balance between memory and logic elements in cost and power sensitive embedded solutions. When system prices are measured in a few euros instead of a few hundred, the large, power intensive and costly memory hierarchy solutions typically used in computer and communications applications are impractical. A multithreading extension to the microprocessor core is especially for deeply embedded systems a more effective approach.Infineon has developed a new processor solution: TriCore 2. It is the second generation of the TriCore Unified Processor architecture. TriCore 2 contains, among others, a block multithreading solution, which responds to the blocking code memory latency in one thread by executing the instructions of a second thread. In this way, the execution pipelines of the processor can be almost fully utilized. From the user programming model, each thread can be seen as one virtual processor.A typical scenario is a cell phone. Here, generally external 16-bit flash memories with a speed of 40 MHz are used while today’s performance requirements expect processors with a clock speed of 300-400 MHz. Because of this discrepancy, up to 80% of the performance can be lost, despite caches. Larger cache sizes and multi-level memory solutions are not applicable for cost reasons.Block multithreading allows system designers to use comparatively smaller instruction caches and slow external memory while still getting the same overall performance. The performance degradation in the cell phone example can be almost eliminated. Even the clock frequency can be reduced. Block multithreading is very efficient for a general CPU based application residing in cache memory and an algorithmic application in the local on-chip memory. This is a characteristic which many deeply embedded processor applications have. Effectively, a separate DSP and CPU can be replaced by a multithreaded hybrid to reduce chip area, tool costs etc. The block multithreading solution also supports a fast interrupt response, required for most deeply embedded applications.The additional costs for this multithreading solution are small. The implementation in TriCore 2 requires a chip area of only 0.3mm2 in 0.13 micron technology. The most obvious costs are caused by the duplicated register files to eliminate the penalty for task switching. Instruction cache and fetch unit need to support multithreading but the overhead is low. Same to other areas that are affected which are traps and interrupt handling, virtual memory, and debug/trace.Apart from multithreading, TriCore 2 has also other highlights. Advanced pipeline technology allows high instruction per cycle (IPC) performance while reaching higher frequencies (400-600 MHz typical) and complying with demanding automotive requirements. The center of the processor’s hierarchical memory subsystem is an open, scalable crossbar architecture, which provides a method for efficient parallel communication to code and data memory including multiprocessor capability.This presentation will describe the root problems in low-cost, low-power embedded systems that require a multithreaded processor solution.Since the core architecture is well-deployed in the demanding automotive market, the first implementation is specified for these requirements like quality and determinism. Working silicon with this implementation is expected for the first quarter of 2004 and will be used as a demonstrator.

In this paper, we examine the distribution and the length of execution units idle cycles for several typical GPGPU applications to direct the energy-saving strategies to capture potential execution units power-gating opportunities. We record the idle durations of the execution units for SMs (Streaming Multiprocessors) including integer units and floating units in SPs (Streaming Processors) and SFUs (Special Function Units). Second, based on the observation of idleness, we study the effectiveness of the execution units power-gating on the leakage energy saving with two simple policies, the immediate power-gating (IPG) and idle detect power-gating (ID-PG). We examine the polices with various parameter settings in order to offer insights on possible gains and losses from the power-gating techniques to enable smarter strategies in future research. The experimental results show that both policies can achieve satisfactory leakage energy saving on execution units. The immediate power-gating can reduct the execution units leakage energy by 84.3% when the break even time is set to 5 cycles and the idle detect power-gating can save 67.1% of the total execution units leakage energy even if the break even time goes up to 20 cycles.

As on-chip cache size has increased considerably in recent high-performance microprocessor technologies, power dissipation and leakage current in SRAM have become critical. High-performance IC designs use multi-port cache memory to provide the needed accessibility and bandwidth. Since the word and bit lines cover the foot-print of the entire cache section, duplicating the word and bit lines for multiple ports results in large silicon area and increases bitline discharge and power dissipation. As technology scales down device size and supply voltages, static power dissipation has emerged as a critical factor in total system power dissipation. In this paper, we present an area-and energy-efficient multi-port cache memory architecture, which employs isolation nodes, local sense amplifiers and dynamic memory partitioning techniques, to facilitate simultaneous multi-port accesses without duplicating bitlines. The proposed cache memory architecture also reduces bitline latency.

In this paper, we study the interdependency between leakage energy and chip temperature in real-time systems. We observe that the temperature variation on chip has a large impact on the system's leakage energy. By incorporating the temperature information, we propose an online temperature-aware leakage minimization algorithm for real-time systems. The basic idea is to run tasks when the system is cool and the workload is high, and put the system into sleep when it is hot and the workload is light. This online algorithm has low run-time complexity and improve the leakage energy saving by 34% on average in both real life and artificial benchmarks over traditional DVS approaches. Finally, our algorithm can be combined with existing dynamic voltage scaling methods to further improve the total energy efficiency

Modern embedded systems are often severely resource-constrained. In current research, the reduction of dynamic power has been the focus. However, with increased chip speed and density in submicron scale, the static (leakage) power consumption has become an increasingly significant fraction of the total. Indeed, a five-fold increase in leakage power per technology generation has been observed. At this pace, leakage power could soon equal dynamic power. In this paper, we investigate scheduling policies to reduce leakage power in real-time systems. We show that with simple scheduling techniques, overall leakage energy can be reduced by an order of magnitude.

Sex dependent mechanical properties of the human mandibular condyle

The transient sensitive trigger (TST) was used to improve the RC delay time of the long interconnection in deep sub-micron process. The conventional TST circuit has a threshold voltage drop during transitions which results in a longer delay time. In this work, modified techniques are proposed to improve the drawbacks of the conventional TST. The new versions have 45-74% delay improvement compared to the conventional TST, simulated using a 0.25 /spl mu/m CMOS process. The proposed circuits can be applied to the receiving of long interconnection signals for high-speed VLSI applications.

Energy, time, and channel evolution in catastrophically disturbed fluvial systems