Design and Performance Analysis of a Fast 4-Way Set Associative Cache Controller using Tree Pseudo Least Recently Used Algorithm

Summary form only given. An approach towards an information theoretic based analysis and design of cache memories is presented. Computer systems usually have a slow main memory and a faster cache memory, usually much smaller than the main memory because of its cost. A somewhat similar situation is present also in Internet servers. A miss happens whenever an item is not found in the cache memory. If so, the item is fetched from the main memory and placed in the cache. A hit is obtained whenever the item is found in the cache. Usually the cost of a miss is several times that of a hit. The goal is to find strategies for the many to one mapping of addresses of the main memory to the cache memory, as well as the replacement strategies. Usual replacement strategies are least recently used, LRU, random replacement, RR, etc. The main goal is to obtain strategies that will optimize the running time of the program under execution. Since almost all programs use branch instructions and loops, some of the information theoretic approaches previously introduced consider the prediction of the result of a branch based on its past behavior. Here a different approach is considered. In particular the opposite case is analysed, i.e. a linear loop that is executed indefinitely. In particular a combined random replacement and least recently used strategy is analyzed. It is shown that this model is equivalent to the one of classifying N objects in M classes with at least c objects in each class, and that this problem gives a generalization of the Ehrenfests' urn model used in statistical thermodynamics in connection with the Boltzmann H-theorem.

Recently, energy dissipation in microprocessors is getting larger, which leads to a serious problem in terms of allowable temperature and performance improvement for future microprocessors. Cache memory is effective in bridging a growing speed gap between a processor and relatively slow external main memory, and has increased in its size. However, energy dissipation in the cache memory will approach or exceed 50% of the increasing total energy dissipation in processors. An important point to note is that, in the near future, static (leakage) energy will dominate the total energy consumption in deep sub-micron processes. This paper describes a code-generation technique that utilizes special instructions for energy reduction. The instructions perform self-invalidation in cache memories, which leads to efficient energy reduction. We developed a source-to-source-code compiler that implements the automatic code-generation. The simulation results of the generated codes show that our techniques can reduce a substantial amount of leakage energy without large performance degradation.

Two performance gaps in the memory hierarchy, between CPU cache and main memory, and main memory and mass storage, will become increasingly severe bottlenecks for computing-system performance. Although it is necessary to increase memory capacity to fill these gaps, power also increases when conventional volatile memories are used. A new nonvolatile memory for this purpose has been anticipated. Storage class memory is used to fill the second gap. Many candidates exist: ReRAM, PRAM, and 3D-cross point type with resistive change RAM. However, nonvolatile last level cache (LLC) is used to fill the first gap. Advanced STT-MRAM has achieved sub-4ns read and write accesses with perpendicular magnetic tunnel junctions (p-MTJ) [1–2]. Furthermore, mature integration processes have been developed and 8Mb STT-MRAM with sub-5ns operation has shown high reliability [3]. Moreover, because of its non-volatility, STT-MRAM can reduce operation energy by more than 81% compared to SRAM for cache [1]. This paper presents STT-MRAM-based last level cache memory (LLC) including MRAM memory core, peripherals and cache logic circuits, using novel power optimization with high-speed power gating (HS-PG),considering processor architectures and cache memory accesses. The STT-MRAM-based cache has high reliability to reduce the write-error rate with novel write-verify-write. Furthermore, a read-modify-write scheme is implemented to reduce active power without penalty. Figure 7.2.1 presents a block diagram of a 4Mb STT-MRAM based cache.

Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors

In current computer memory system hierarchy, registers and cache are both used to bridge the reference delay gap between the fast processor(s) and the slow main memory. While registers are managed by the compiler using program flow analysis, cache is mainly controlled by hardware without any program understanding. Due to the lack of coordination in managing these two memory structures, significant loss of system performance results because:

Random Access Memory plays a crucial role in data processing in various computing systems for faster applications. A processor always fetches the data from the main memory for processing, sometimes the same data may be required for the processing and need to be fetched repeatedly from the main memory results time consuming. Cache memory supports faster data storage and access by storing instances of programs and data which is routinely accessed by the processor. Therefore, the cache memory is used to store recently fetched data and when a processor requests to fetch the data the controller will first check the data in cache, if the fetched data is there in the cache then it will be fetched otherwise the controller will fetch the data from the main memory. Therefore, the cache memory is useful for improving speed of processing without wasting much time for fetching the repeated data. This paper deals with various structures of single ended S-RAM cells and proposes a novel three transistor S -RAM cell design Using Tanner 45nm Technology.

Nonvolatile random access memory (NVRAM) is becoming a popular alternative as the memory and storage medium in battery-powered embedded systems because of its fast read/write performance, byte-addressability, and nonvolatility. A well-known example is phase-change memory (PCM) that has much longer life expectancy and faster access performance than NAND flash. When NVRAM is considered as both main memory and storage in battery-powered embedded systems, existing page cache mechanisms have too many unnecessary data movements between main memory and storage. To tackle this issue, we propose the concept of “union page cache,” to jointly manage data of the page cache in both main memory and storage. To realize this concept, we design a partial page cache strategy that considers both main memory and storage as its management space. This strategy can eliminate unnecessary data movements between main memory and storage without sacrificing the data integrity of file systems. A series of experiments was conducted on an embedded platform. The results show that the proposed strategy can improve the file accessing performance up to 85.62% when PCM used as a case study.

Many schemes had been used to reduce the performance (or speed) gap between processors and main memories; such as the cache memory is one of the most methods. In this paper, we issue the structure of shared cache, which is based on the multiprocessor architectures to reduce the memory latency time that is the one of major performance bottlenecks of modern processors. In this paper, we mix two schemes, sharing cache and multithreading, to implement this proposed multithreaded architecture with shared cache, to reduce the memory latency and, furthermore improve the processor performance. In this proposed multithreaded architecture, the shared cache is achieved in level-1 (L1) data cache. The L1 shared data cache is combination of cache clock in the single space address and a cache controller to solve the required data transmitting, data copies simultaneously, and reduce memory latency time.

Optimal cache usage for separable image processing algorithms on general purpose workstations

Cache memory hierarchies are used to buffer those portions of main memory with the most frequent use by the CPU. As cache memory is very costly, good design techniques must consider small cache sizes maintaining high levels of use (hit ratio) and ease of implementation. The memory replacement policy is important in maintaining a high hit ratio. Most replacement policies used are easily implemented when the main memory has fixed page locations. A new cache algorithm using a variable page configuration is explained in terms of program behaviour.

Global load instruction aggregation based on dimensions of arrays

Cache memories are traditionally disabled in space-level and safety-critical applications, since it was believed that the sensitive area they introduce would compromise the system reliability. As technology has evolved, the speed gap between logic and main memory has increased in such a way that disabling caches slows the code much more than in the past. As a result, the processor is exposed for a much longer time in order to compute the same workload. In this paper we demonstrate that, on modern embedded processors, enabling caches may bring benefits to critical systems: the larger exposed area may be compensated by the shorter exposure time, leading to an overall improved reliability. We describe the Mean Workload Between Failures, an intuitive metric to evaluate the impact of enabling caches for a given generic application error rate. The proposed metric is experimentally validated through an extensive radiation test campaign using a 28 nm off-the-shelf ARM-based SoC as a case study. The failure probability of the bare-metal application is decreased when the L1 cache is enabled but increased when L2 is also enabled. We also discuss when L2 caches could make the device more reliable.

A 70‐MHz, 32‐bit BiCMOS processor has been developed. This paper describes the architecture and the high‐speed technology, mainly the arithmetic unit, of the very‐high‐speed BiCMOS processor. This processor includes a 32‐bit ALU, register file with four ports, arithmetic unit composed of ±32‐bit barrel shifter and so on, ROM storing microprograms, memory management unit, cache controller, and clock generator. The chip integrates 529,000 transistors (including bipolar transistors of 1.5 percent) within 12.98 mm × 12.98 mm chip. The BiCMOS circuit technology is applied to the register file, arithmetic circuit, clock generator, and so on, to achieve the 70‐MHz BiCMOS processor under typical conditions. Thus, the effectiveness of employing the BiCMOS technology for very‐high‐speed digital LSIs, such as microprocessors, has been verified.

In this paper, we exploit the concept of sequential way access to reduce the number of ways being activated on each access of set-associative cache for low energy consumption while maintaining performance. The proposed architecture accesses each way in sequence, and then eliminates subsequent accesses if a hit is detected. It features smart cache placement and replacement policies to minimize the number of required access cycles. It can also reduce the heavy fanout load of the hit-signal, which suppresses the possible increase of cache cycle time due to more complicated cache control mechanism. The experimental results show that a 32 KB 2-way sequential way-access set-associative cache reduces the energy consumption by 24% compared against a conventional 2-way set-associative cache with the same size at virtually no performance loss.

An ad-hoc network will often change rapidly in topology, this courses for routes in the network to often disappear and new to arise. The Ad-hoc On-Demand Distance Vector Routing Protocol(AODV), is based on the principle of discover routes as needed. In this paper we will extend the definition of AODV with the ability to discover multiple routes to a host and switch between them, if an active route is becoming weak and there is a risk that it will disappear. We will refer to it as "pre-emptive AOMDV". We will show that the performance of pre-emptive AOMDV do handle changes in topology better than AODV it self. To show the effect of extending AODV, the suggested protocol is implemented in a simulator. Performance enhancements will be presented from different scenarios, to compare pre-emptive AOMDV with the ordinary AODV. In this paper we also focus on intrusion detection based on Finite State Machine and cache memory in ad hoc networks. Security is one of the most important issues in current networks. The most common cases of attacks in mobile Ad hoc networks can be drop of routing packets and changes in the incoming packets which aims at disrupting the network routing and overall network reduce performance. The presented approach based on FSM focuses at recognizing the malicious nodes within the network in a fast and accurate way, then it deals with rapid introduction of the malicious nodes to other nodes in the network to prevent sending multiple packets and drop and packet change. Finally, we will show the significant improvement in comparison with others, we simulated our methods by NS2 software.