Speed Indicators for Circuit Optimization

A perimeter gated SPAD (PGSPAD), a SPAD with an additional gate terminal, prevents premature perimeter breakdown in standard CMOS SPADs. At the same time, a PGSPAD takes advantage of the benefits of standard CMOS. This includes low cost and high electronics integration capability. In this work, we simulate the effect of the applied voltage at the perimeter gate to develop a consistent electric field distribution at the junction through physical device simulation. Additionally, the effect of the shape of the device on the electric field distribution has been examined using device simulation. Simulations show circular shape devices provide a more uniform electric field distribution at the junction compared to that of rectangular and octagonal devices. We fabricated PGSPAD devices in a sub-micron process (0.5 μm CMOS process and 0.5 μm high voltage CMOS process) and a deep-submicron process (180 nm CMOS process). Experimental results show that the breakdown voltage increases with gate voltage. The breakdown voltage increases by approximately 1.5 V and 2.5 V with increasing applied gate voltage magnitude from 0 V to 6 V for devices fabricated in 0.5 μm and 180 nm standard CMOS process respectively.

A standard CMOS optical interconnect is proposed, including an octagonal-annular emitter, a field oxide, metal 1-PSG/BPSG-metal 2 dual waveguide, and an ultra high-sensitivity optical receiver integrated with a fingered P+/N-well/P-sub dual photodiode detector. The optical interconnect is implemented in a Chartered 3.3-V 0.35-μm standard analog CMOS process with two schemes for the research of the substrate noise coupling effect on the optical interconnect performance: with or without a GND-guardring around the emitter. The experiment results show that the optical interconnect can work at 100 kHz, and it is feasible to implement optical interconnects in standard CMOS processes.

In this paper a set of high-speed differential pad cells are presented. The pad cells are designed to work with the IEEE Draft Standard for Low-Voltage Differential Signals for Scalable Coherent Interface (SCI-LVDS) [4]. The standard sets specifications for high-speed point to point communication between complex subcircuits in digital systems. The pad cells are in compliance with the draft, but are designed to operate up to at least 500 MHz instead of the 250 MHz proposed in the draft. The pad cells presented in this paper are designed in a standard 1µm CMOS process using standard DIL packaging. This has proved possible despite the electrical specifications being narrowed as a result of the doubling of the operating frequency. The circuit has ESD protection and utilizes internal termination with a single external impedance reference and thereby facilitates ease of use and higher package density.

A vibration sensor with floating gate based on standard CMOS and post-CMOS processes is presented. The vibrating membrane is released with one simple metal sacrificial layer removal step, which is very cost-efficient and fully CMOS compatible, enabling monolithic integration of circuitry. Test results show that the proposed sensor can work properly, and have good frequency linearity with the test shaking system, which exhibits prefect linearity up to 99.94%.

Deep sub-micron chip development

The transient sensitive trigger (TST) was used to improve the RC delay time of the long interconnection in deep sub-micron process. The conventional TST circuit has a threshold voltage drop during transitions which results in a longer delay time. In this work, modified techniques are proposed to improve the drawbacks of the conventional TST. The new versions have 45-74% delay improvement compared to the conventional TST, simulated using a 0.25 /spl mu/m CMOS process. The proposed circuits can be applied to the receiving of long interconnection signals for high-speed VLSI applications.

We propose a high-voltage switch driven by wavelength-modulated light, which is suitable for remote MEMS (especially electrostatic actuators) device operation. It is fabricated on an SOI wafer and consists of series-connected n-MOSFETs whose substrates are mesa-isolated, allowing the switch to endure a high voltage. The fabrication process requires no modification in a standard CMOS process itself, which is easy for foundries to accept. In addition, by using wavelength-modulated light instead of electric circuits for the control of the switch, it achieves a simple, scalable, small switching circuit regardless of the switching voltage. Fabrication and operation of 50 V switch using 5 V standard CMOS technology is reported in this paper.

Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%. >

In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V DD = 0.9 V, approximately 10% higher peak power efficiency at V DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.

Leakage current is the main source of power dissipation in low-frequency digital circuits implemented in deep submicron processes. This contribution introduces a novel active-mode leakage reduction technique for ultra-low-power (ULP) low-frequency applications. It is based on the ULP CMOS logic style achieving negative-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> self-biasing ULP logic gates have static current reduced by several orders of magnitude. For a commercial 0.13-μm technology, power consumption of ULP gates at low frequencies is lower than standard CMOS counterparts even considering high-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> devices, subthreshold operation and reverse body biasing. ULP gates are shown to be very stable against process, voltage and temperature variations.

A fully integrated transmit chain for 802.11a band with on-chip power amplifier and on-chip balun matching network in 45 nm standard digital CMOS process demonstrates saturated power of +23 dBm. The average efficiency is +5% and peak efficiency is +15%. A standalone class AB CMOS power amplifier with on-chip balun matching network was also produced and detailed characterization data is presented. Using digital predistortion, an EVM of -28 dB is achieved at 19 dBm for 5 GHz band and 2.5 GHz band for standalone power amplifier.

In this paper, we discuss the advantages and limitations of using standard CMOS fabrication processes for the design of integrated affinity-based biosensor systems. In particular, we examine the compatibility of CMOS with various assaying techniques and the possibility of fabricating their transducer structures.

The Elmore base delay calculation method has long been in use, but this method cannot meet accuracy demands of current designs using deep sub-micron processes. On the other hand, SPICE can provide high accuracy, but it is very time consuming. Therefore, a novel, highly accurate and high-speed delay analysis method is proposed: MOR (model order reduction). We applied it in interconnect signal analysis to evaluate its performance

TCAD has contributed to processldevice design and prediction of the device performances for decades. This role is still very important in very deep submicron process; however, new aspect in the semiconductor industry has arisen. Interconnect issue becomes more critical in SoC timing closure. ITRS roadmap predicts future of processldevices and interconnects, which lead to a standardized process and device. TCAD seems to be requested to contribute in the new situation of SoC era. The panel addresses topics such as: What is the new role of TCAD in SoC era? How TCAD can contribute towards the ultimate-solution in timing closure problem. How to attack SI(Signa1 Integrity) Physical Design by TCAD. Can TCAD make innovation on Process & Device, which changes the ITRS2001?

Digital single event transients induced in combinatorial logic are quickly becoming a significant error source as circuit feature sizes shrink and digital circuits operate faster. In this paper, we are able to compare the combinatorial logic error rate to the sequential logic error rate in both heavy ion and proton environments in a simple digital circuit created in a 0.18 /spl mu/m CMOS technology. We are able to do this by comparing data from two unique test chips.