Switched-current circuit design issues

For applications requiring low-voltage low-power and real-time processing, a novel scheme for the VLSI implementation of wavelet transform (WT) using switched-current (SI) circuits is presented. SI circuits are well suited for these applications since the dilation constant across different scales of the transform can be implemented, and controlled by both the aspect-ratio of the transistors and the clock frequency. The quality of such implementation depends on the accuracy of the corresponding wavelet approximation. First, an optimized procedure based on differential evolution algorithm (DE) is applied to approximate the transfer function of a linear steady-state system whose impulse response is the required wavelet. The proposed approach significantly improves the accuracy of approximation wavelets. Next, the approximation of time-domain wavelet function is implemented by the SI analog filters. Finally, the design of the complete SI filter based on first-order and biquad section as main building block is detailed. Simulations demonstrate the performance of the proposed approach to analog WT implementation.

In this paper, digital CMOS switched-current (SI) circuits with low charge-injection errors are presented. These circuits are based on the operation of the switches at virtual-ground nodes to result in signal-independent charge injection. Based on this scheme, different topologies for the memory cell are discussed. To verify the theoretical concepts developed, a third-order elliptic low-pass SI filter is implemented in a 0.25-/spl mu/m digital CMOS process. The filter nominally operates with a clock frequency of 10 MHz, cutoff frequency of 1 MHz, and a power supply of 2.3 V, while consuming 29 mW of power and processing input signals as large as 600-/spl mu/A peak differential. The low-charge injection nature of the circuit is reflected in its low total harmonic distortion of -59 dB for a 0.3-MHz signal with a modulation index of 0.5.

The paper provides a new approach to an efficient reduction of switching noise in switched-current (SI) circuits. This approach makes use of a noise-free current-mode switch that can cut itself off to shield a circuit node, at which the voltage needs to be preserved precisely, from switching noise. With this approach, a reduction rate of more than 90% can be achieved. This approach can be very easily implemented. It does not require any special fabrication process, area-consuming components, matching devices, or complex clocks. This work can lead to a significant improvement of the operation quality of SI circuits without sacrificing speed and power dissipation.

Based on possible defects on the layout of a practical non-ideal switch, fault model and test generation of current copiers, basic building block of switched-current circuits, are presented in this study. We consider two types of switches, current switches and voltage switches, which have been commonly used in both switched-current circuits and switched-capacitor circuits, and both catastrophic and non-catastrophic faults of transistors used as switches. The generated test sequence achieve full testability of current copiers. The tester and test process are readily applied for any switched-current circuits.

This paper describes a theoretical study of the main errors in switched-current (SI) cells, such as conductance ratio error, settling time error and charge injection error, and their influence on the output/input transfert characteristic. First, our interest is focused on the study each error mechanism and its effect on the SI memory cell. After that, we studied the influence of their cumulative effect. Finally, we detailed the effect of cumulative error on the integrator level. The most significant non-idealities of SI cell are identified and their cumulative effect on SI cell and SI integrator transfert characteristic are analytically demonstrated.

This chapter will examine the effects of electrical noise on a switched current circuit. Here electrical noise means the small fluctuations of current in an MOS transistor and is inherent to the operation of the device. Often the term electrical noise is used to describe any unwanted signal, including power supply disturbances and parasitic coupling of extraneous digital signals into the analogue signal path. While disturbances by these unwanted signals may also corrupt the operation of a switched-current circuit, they can be greatly reduced and practically eliminated by the use of careful layout techniques and by using balanced circuits.

This paper introduces a Switched-current Analysis Program (SIAP) that can perform both transient and frequency domain analysis of switched-current (SI) circuits. The program uses sparse matrices to reduce storage requirements and computation time. Transient analysis is performed using the large signal MOSFET model and the frequency domain analysis uses the small signal MOSFET model that includes all parasitic capacitance. All devices are modeled in a manner comparable with HSPICE and include almost all nonidealities, such as nonideal switches, clock feedthrough, channel-length modulation and transistor parasitic capacitors. Multiple inputs are allowed in both the transient and frequency domain analysis, thus differential circuits can be easily analyzed.

A switched-current fuzzy processor for pattern recognition is proposed. It accepts multiple inputs that represent multiple features of an unknown pattern in a time-shared way. Membership function generators generate memberships corresponding to each standard pattern according to the input features, then different weights are used for different feature memberships. Switched-current accumulators accumulate multiple weighted memberships to get synthetic memberships. Finally, a MAX circuit finds the maximum synthetic membership and the recognition result is obtained. In this system, all the analog circuits employed are current-mode and switched-current mode circuits, so that the system can be directly fabricated in standard digital CMOS technology, and can be easily integrated into a mixed analog-digital system.

In this paper, we presents the comparison of second-order sigma-delta modulator (SDM) with switched-capacitor (SC) and switched-current (SI) techniques. In the voltage-mode, we use the switched-capacitor parasitic-insensitive integrator to implement this modulator, but in the current-mode we use sample-and-hold circuit which not only consists of a feedback circuit to reduce the impedance at the input but also with a common-mode feedforward (CMFF) circuit to improve the common-mode offset at the output. The presented second-order sigma-delta modulators simulate with the parameters of the TSMC 0.35 mum CMOS process technology. The simulated results of SC and SI techniques show that the maximum signal-to-noise ratio (SNR) is 89 dB and 86.3 dB, respectively, which are about equal to 14 bits resolution with conditions that the sampling rate is 10.24 MHz, the oversampling ratio is 128, and the consumption is 12 mW.

A high-speed fully differential current switch is presented. The clock-feedthrough effect is reduced by Swing-Reduced Drivers (SRDs) and neutralized by dummy transistors. With the use of SRDs, less charges are required to be transferred to/from the gates of the switching transistors, and hence, the switching speed can be increased without significant output error. The SRDs also reduce the possible large current spikes on the outputs of the current switch. Analysis shows this current switch is ideal for high-speed current-mode signal processing. A continuous-time switched-current /spl Sigma//spl Delta/ modulator using these current switches has been implemented in a 2 /spl mu/m CMOS process and achieved a 50 dB dynamic range with a 50 MHz clock.

Design automation of a lossless multiport network and its application to image filtering

Capacitive current switching has become increasingly necessary for power factor correction in distribution systems. However, Restrikes are potentially dangerous as they could cause overvoltage which can be harmful to the power system. The dielectric strength of the Vacuum Interrupter (VI) in a capacitive current switching is strongly determined by a condition of the contact surfaces modified by an inrush current. But the influence of the inrush current on restrike phenomenon of VIs is still not well understood. The objective of this paper is to understand the restrike characteristics of VI under the inrush currents of different amplitudes. The peak values of inrush currents are set at 0kA, 2kA, 5kA and 10kA. VIs with a rated voltage of 7.2kV are used. For the each testing operation, VI suffers an inrush current during a making operation. Then a DC recovery voltage appeared across the vacuum interrupters after a switching current (lower than 1 A) is interrupted. The experimental results show that a higher inrush current induces more damages to the contact surfaces, which result in more restrikes. The restrike probabilities are 4.6%, 17.9% and 30.4% on average at the inrush current of 0kA, 2kA and 5kA respectively. VIs cannot be opened after several test operations by a welding at the inrush current of 10kA. The inrush currents with higher amplitude induce the restike occurring earlier than that of lower amplitude during the recovery voltage.

This article presents architectures and circuit techniques to design chaotic piecewise-linear discrete maps in CMOS VLSI. Maps are presented for white and 1/fγ noise generation, as well as to display bidimensional strange attractors. The proposed circuits use only MOS transistors and thus are suitable for implementation in standard CMOS technologies containing only one poly layer. A family of CMOS building blocks for piece-wise-linear function interpolation in current-domain is presented based upon the use of a current switch. Novel circuit strategies are given for improved current-switch performance as well for high-resolution current comparison. These strategies can be used for the design of chaotic current-mode circuits, as well for the representation problem via basis functions in feedforward neural networks and fuzzy inference engines. Also, an innovative scheme for adaptive feedthrough cancellation in dynamic current mirrors is presented, which aids in reducing the most significant error source in chaotic current-mode discrete maps. The article includes experimental results from monolithic n-well CMOS 1.6 μm prototypes of the building blocks as well as complete systems; in particular, a chaotic neuron according to the Aihara's model and a broadband white noise generator.

A low power current controllable single-input three-output current-mode filter using MOS transistors only

CMOS active-pixel image sensors, as well as charge-coupled devices, generate both white noise and 1/f/sup /spl alpha//-noise over several decades depending on biasing current, operating temperature, and the characteristics of the process used, limiting the detector dynamic range. Three readout circuits, based on a fully differential cascode operational transconductance amplifier, designed and realized on a standard CMOS 0.7-/spl mu/m single polysilicon/double metal process, are proposed for CMOS active-pixel imagers. The first is an uncompensated switched capacitor (SC) voltage amplifier; the second, an offset compensated SC amplifier; and the third, a commutable bandpass filter. All three amplifiers allow correlated double sampling and double delta sampling for pixel and column fixed pattern noise suppression, respectively. The amplifiers offer up to 10-Mpixels/s readout rates. A detailed theoretical analysis of the amplifiers response to white noise and low-frequency excess noise is given, considering nonstationary nature of the output signals. An original method based on diffusive Markovian representation of 1/f/sup /spl alpha//-noise is used. The theoretical results are compared with experimental data.