Analog VLSI implementation of wavelet transform using switched-current circuits

Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%. >

In this paper, digital CMOS switched-current (SI) circuits with low charge-injection errors are presented. These circuits are based on the operation of the switches at virtual-ground nodes to result in signal-independent charge injection. Based on this scheme, different topologies for the memory cell are discussed. To verify the theoretical concepts developed, a third-order elliptic low-pass SI filter is implemented in a 0.25-/spl mu/m digital CMOS process. The filter nominally operates with a clock frequency of 10 MHz, cutoff frequency of 1 MHz, and a power supply of 2.3 V, while consuming 29 mW of power and processing input signals as large as 600-/spl mu/A peak differential. The low-charge injection nature of the circuit is reflected in its low total harmonic distortion of -59 dB for a 0.3-MHz signal with a modulation index of 0.5.

The paper provides a new approach to an efficient reduction of switching noise in switched-current (SI) circuits. This approach makes use of a noise-free current-mode switch that can cut itself off to shield a circuit node, at which the voltage needs to be preserved precisely, from switching noise. With this approach, a reduction rate of more than 90% can be achieved. This approach can be very easily implemented. It does not require any special fabrication process, area-consuming components, matching devices, or complex clocks. This work can lead to a significant improvement of the operation quality of SI circuits without sacrificing speed and power dissipation.

Based on possible defects on the layout of a practical non-ideal switch, fault model and test generation of current copiers, basic building block of switched-current circuits, are presented in this study. We consider two types of switches, current switches and voltage switches, which have been commonly used in both switched-current circuits and switched-capacitor circuits, and both catastrophic and non-catastrophic faults of transistors used as switches. The generated test sequence achieve full testability of current copiers. The tester and test process are readily applied for any switched-current circuits.

This paper describes a theoretical study of the main errors in switched-current (SI) cells, such as conductance ratio error, settling time error and charge injection error, and their influence on the output/input transfert characteristic. First, our interest is focused on the study each error mechanism and its effect on the SI memory cell. After that, we studied the influence of their cumulative effect. Finally, we detailed the effect of cumulative error on the integrator level. The most significant non-idealities of SI cell are identified and their cumulative effect on SI cell and SI integrator transfert characteristic are analytically demonstrated.

The differential evolution (DE) algorithm is a new heuristic approach with three main advantages: it finds the true global minimum of a multimodal search space regardless of the initial parameter values, it has fast convergence, and it uses only a few control parameters. The DE algorithm, which has been proposed particularly for numeric optimization problems, is a population-based algorithm like the genetic algorithms and uses similar operators: crossover, mutation, and selection. In this work, the DE algorithm has been applied to the design of digital finite impulse response filters, and its performance has been compared to that of the genetic algorithm and least squares method.

Evolutionary computational techniques have been employed judiciously in various signal processing applications of late. In this paper, such an attempt has been made to design a low-pass linear-phase multiplier-less finite duration impulse response (FIR) filter using differential evolution (DE) algorithm. This particular evolutionary optimization technique has been explored to search the impulse response coefficients of the FIR filter in the form of sum of power of two (SPT) in order to avoid the multipliers during design process. The performance of the designed low-pass filter has been studied thoroughly in terms of its frequency characteristics and primitive requirement of fundamental hardware blocks. The superiority of our design has been ascertained over a number of existing techniques by various means. Finally, the proposed filter of different lengths has been implemented on a field programmable gate array (FPGA) chip for evaluating the competency of this work. The percentage improvement in hardware complexity produced by our design has also been computed and clearly listed in this paper for convenience.

This paper introduces a Switched-current Analysis Program (SIAP) that can perform both transient and frequency domain analysis of switched-current (SI) circuits. The program uses sparse matrices to reduce storage requirements and computation time. Transient analysis is performed using the large signal MOSFET model and the frequency domain analysis uses the small signal MOSFET model that includes all parasitic capacitance. All devices are modeled in a manner comparable with HSPICE and include almost all nonidealities, such as nonideal switches, clock feedthrough, channel-length modulation and transistor parasitic capacitors. Multiple inputs are allowed in both the transient and frequency domain analysis, thus differential circuits can be easily analyzed.

Transfer function estimation of turboalternator from practical operating data by spectral analysis

To meet the requirement of low power consumption in biomedical implantable pacemaker applications, a novel method based on balanced log-domain wavelet transform (WT) circuits has been developed for detecting QRS complexes of cardiac signals. By using a hybrid particle swarm optimization algorithm (PSO) combined with sequential quadratic programming, an excellent approximation of the first derivative of a Gaussian wavelet is achieved. The WT circuits are composed of filters whose impulse response is the approximation of the Gaussian wavelet. The WT filter design is based on a time inverse follow-the-leader feedback structure with class-AB balanced log-domain integrators as the main building blocks. HSPICE simulation shows that the power consumption is only 62 nW per scale for a 1.2 V supply, and the dynamic range is 86 dB for 2% total harmonic distortion. The high accuracy of the QRS complex detection method has been validated using the MIT-BIH database.

The authors present a fourth-order bandpass ΣΔ switched-current modulator IC in 0.8 µm CMOS single-poly technology. It is the first reported integrated circuit realisation of a bandpass ΣΔ modulator using switched-current circuits. Its architecture is obtained by applying a lowpass to bandpass transformation (z-1 → – z-2) to a second-order lowpass modulator. It has been realised using fully-differential circuitry with common-mode feedback. Measurements show 8 bit dynamic range up to 5 MHz clock frequency.

The design of high-speed FIR (finite impulse response) filters using switched-current technology is considered. By using current to represent signals, an FIR filter has been implemented using building blocks developed from switched-current circuits. It has been fabricated using the MOSIS 2- mu m CMOS technology, and can operate at a sampling frequency over 10 MHz. >

On the dynamic system identification of the response behaviour of linear viscoelastic materials

We investigated the prediction of side-channel leak-age on the power delivery network (PDN) outside a cryptographic IC. To predict the leakage, it is necessary to estimate the switching current caused by the switching activity. So far, high temporal resolution estimation based on gate-level logic simulation has been proposed, but due to the decoupling property of the PDN, the switching current leaking out of the IC chip attenuates signif-icantly. Therefore, this paper calculates the mean of the switching currents over the clock period based on register transfer level (RTL) logic simulation, and then approximates it into a triangle waveform. This approach enables us to simulate the switching current faster than with gate-level simulation. In addition, the simulation time is further shortened by calculating the switching current only to the targeted round of a cryptographic algorithm (AES). Switching currents of the previous rounds were given as statistical models with the same sample mean and variance as the targeted round. As a result of simulating the switching current of an FPGA with the proposed method, we were able to obtain the low-order harmonic components of the current in almost the same magnitude as the gate-level simulation. We also simulated correlation power analysis (CPA) results for the printed circuit board on which the FPGA with the AES circuit was mounted, and found that the proposed method could predict the dynamic power supply voltage observed on the board and CPA results with sufficient accuracy.

This chapter considers the approximation of the transfer function of a linear system in terms of a causal filter bank. Assume that \(f\left( {{\rm{e}}^{{\rm{i}}\theta } } \right)\) with \(\theta \in [-\pi,\pi)\) is the transfer function of an arbitrary discrete-time linear system \({\cal L}\), and let \(\Phi = \left\{ {\varphi _k } \right\}_{k = 1}^\infty \) be a set of transfer functions of an orthonormal filterbank. It is assumed that f as well as all \(\varphi_{k}\) are elements of a certain Banach algebra \({\cal B}\) which characterizes the system theoretical properties of \({\cal L}\) and of the filterbank \(\Phi \). Moreover, since f as well as \(\{\varphi_{k}\}^{\infty}_{k=1}\) should represent causal systems, these transfer functions have to belong to the causal subspace \({\cal B}_ + \,{\rm{of}}\,{\cal B}\). Then, it is desirable to obtain an approximation of f in this filterbank of the form