Switched-current circuits in digital CMOS technology with low charge-injection errors

Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%. >

For applications requiring low-voltage low-power and real-time processing, a novel scheme for the VLSI implementation of wavelet transform (WT) using switched-current (SI) circuits is presented. SI circuits are well suited for these applications since the dilation constant across different scales of the transform can be implemented, and controlled by both the aspect-ratio of the transistors and the clock frequency. The quality of such implementation depends on the accuracy of the corresponding wavelet approximation. First, an optimized procedure based on differential evolution algorithm (DE) is applied to approximate the transfer function of a linear steady-state system whose impulse response is the required wavelet. The proposed approach significantly improves the accuracy of approximation wavelets. Next, the approximation of time-domain wavelet function is implemented by the SI analog filters. Finally, the design of the complete SI filter based on first-order and biquad section as main building block is detailed. Simulations demonstrate the performance of the proposed approach to analog WT implementation.

The paper provides a new approach to an efficient reduction of switching noise in switched-current (SI) circuits. This approach makes use of a noise-free current-mode switch that can cut itself off to shield a circuit node, at which the voltage needs to be preserved precisely, from switching noise. With this approach, a reduction rate of more than 90% can be achieved. This approach can be very easily implemented. It does not require any special fabrication process, area-consuming components, matching devices, or complex clocks. This work can lead to a significant improvement of the operation quality of SI circuits without sacrificing speed and power dissipation.

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors complicates the use of feedback circuits. Thus feedback is generally not used in the front-end of our digital process CMOS receivers.

Based on possible defects on the layout of a practical non-ideal switch, fault model and test generation of current copiers, basic building block of switched-current circuits, are presented in this study. We consider two types of switches, current switches and voltage switches, which have been commonly used in both switched-current circuits and switched-capacitor circuits, and both catastrophic and non-catastrophic faults of transistors used as switches. The generated test sequence achieve full testability of current copiers. The tester and test process are readily applied for any switched-current circuits.

Passive mixer with OPA filter for DVB-H front-end in 65 nm digital CMOS technology

This paper describes a theoretical study of the main errors in switched-current (SI) cells, such as conductance ratio error, settling time error and charge injection error, and their influence on the output/input transfert characteristic. First, our interest is focused on the study each error mechanism and its effect on the SI memory cell. After that, we studied the influence of their cumulative effect. Finally, we detailed the effect of cumulative error on the integrator level. The most significant non-idealities of SI cell are identified and their cumulative effect on SI cell and SI integrator transfert characteristic are analytically demonstrated.

In this paper, a heuristic methodology for design of highly linear MOSFET capacitors (MOSCAPs) has been presented. For a certain amount of accessible chip area, the proposed algorithm intends to find the structure which has the least C-V variation. It uses a modified version of the genetic programming to optimize the capacitor topology and transistors' dimensions. To test the performance of the algorithm, it was utilized for obtaining a highly linear 1 pF capacitor, i.e. with less than 3% variation of capacitance versus 1 V variation across the MOSCAP structure terminals, in a commercial 0.18 mum standard digital CMOS technology. This level of linearity can be otherwise achieved only with MIM capacitors, which are not available in digital CMOS processes.

This paper presents a low-offset, low-power, high-speed comparator using bulk biasing calibration technique. The adjustment of bulk voltage is realized by analog integration in a feedback loop. The technique can calibrate the offset voltage to small value without reducing speed. The comparator is designed in a standard digital 65nm CMOS technology with 1V supply voltage. The comparator works at 1GHz clock frequency. Simulation results show that it achieves 1.2 mV offset voltage and 1.1mV input referred RMS noise, while dissipating 14fJ/comparison.

A power-efficient and low-cost 1.0625–3.125 Gb/s serial transceiver is presented in this paper for Fiber Channel (FC), Peripheral Component Interconnect Express (PCIe), and RapidIO applications. To support multiple standards with a single low power and low cost design, the transceiver presented here uses a wide swing range source-series-terminated (SST) transmitter (TX), a passive receiver (RX) equalizer, a dual-loop phase locked loop (PLL) and a mixed signal clock and data recovery (CDR) unit. The proposed SST transmitter also realizes a 3bit 2-tap de-emphasis filter that compensates up to 6 dB on the transmitter, and a passive equalizer that achieves 4 dB transmission in the receiver. The dual-loop PLL with an on-chip regulator is used to generate a low-jitter clock for the TX and CDR’s reference. A CDR with a phase interpolator (PI) is proposed with a mixed signal structure to recover the clock on the RX and it can tolerate a frequency offset of up to 2000 ppm. The transceiver is fabricated in a 130 nm digital CMOS process and occupies an area of 0.8 mm2. With supply voltages of 1.2 V and 3.3 V, the transceiver dissipates 78 mW when compensating for a total loss of 10 dB at 3.125 Gb/s.

This paper describes the architecture and circuit design of an experimental 8-b differential 15 MS/s CMOS A/D converter, implemented using the switched-current (SI) technique. Particular emphasis has been given to maintaining analog bandwidth and hence the effective number of bits right across the input Nyquist band. Individual cells have also been optimized for inherent accuracy to achieve good performance in a simple uncorrected conversion algorithm. The converter is fabricated in a standard 0.8 /spl mu/m 5 V digital CMOS process and occupies 2.4 mm/sup 2/.

A 34–40 GHz VCO fabricated in 65 nm digital CMOS technology is demonstrated in this paper. The VCO uses a combination of switched capacitors and varactors for tuning and has a maximum Kvco of 240 MHz/V. It exhibits a phase noise of better than −98 dBc/Hz @ 1-MHz offset across the band while consuming 12 mA from a 1.2-V supply, an FOM T of −182.1 dBc/Hz. A cascode buffer following the VCO consumes 11 mA to deliver 0 dBm LO signal to a 50Ω load.

A switched-current fuzzy processor for pattern recognition is proposed. It accepts multiple inputs that represent multiple features of an unknown pattern in a time-shared way. Membership function generators generate memberships corresponding to each standard pattern according to the input features, then different weights are used for different feature memberships. Switched-current accumulators accumulate multiple weighted memberships to get synthetic memberships. Finally, a MAX circuit finds the maximum synthetic membership and the recognition result is obtained. In this system, all the analog circuits employed are current-mode and switched-current mode circuits, so that the system can be directly fabricated in standard digital CMOS technology, and can be easily integrated into a mixed analog-digital system.

An experimental 6.4 MS/s CMOS A/D converter design is presented. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to realize a 1.5-b/stage pipelined architecture. High sampling rate and large input bandwidth were the main design objectives. The complete ADC was simulated using a SPICE level simulator. Performance is verified by analyzing the FFT of 2048 simulated samples. With f/sub in/=3.05 MHz, the simulated SFDR=62.7 dB and SNDR=57 dB. Simulations also indicate more than 6.7 effective number of bits at f/sub in/=15.85 MHz. Thus a high input signal bandwidth is demonstrated. Power dissipation is estimated to be less than 90 mW from a 3.0 V supply. Die area is 2.7 mm/sup 2/ when implemented in a 0.8 /spl mu/m digital CMOS process.

Switched-current oversampling A/D converters are the ideal choice for mixed analog/digital design due to their complete compatibility with digital CMOS process and high tolerance to process variation. This paper presents a tutorial discussion on all the aspects of switched-current oversampling A/D converters, including structures, circuits, and practical issues. Three different modulator structures and six different types of switched-current circuits were used with an emphasis on low-voltage operation. Eight 3.3-V oversampling A/D converters were implemented and measured, and another one 1.2-V oversampling A/D converter was also implemented but yet to be measured.