Test generation of analog switched-current circuits

Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%. >

For applications requiring low-voltage low-power and real-time processing, a novel scheme for the VLSI implementation of wavelet transform (WT) using switched-current (SI) circuits is presented. SI circuits are well suited for these applications since the dilation constant across different scales of the transform can be implemented, and controlled by both the aspect-ratio of the transistors and the clock frequency. The quality of such implementation depends on the accuracy of the corresponding wavelet approximation. First, an optimized procedure based on differential evolution algorithm (DE) is applied to approximate the transfer function of a linear steady-state system whose impulse response is the required wavelet. The proposed approach significantly improves the accuracy of approximation wavelets. Next, the approximation of time-domain wavelet function is implemented by the SI analog filters. Finally, the design of the complete SI filter based on first-order and biquad section as main building block is detailed. Simulations demonstrate the performance of the proposed approach to analog WT implementation.

In this paper, digital CMOS switched-current (SI) circuits with low charge-injection errors are presented. These circuits are based on the operation of the switches at virtual-ground nodes to result in signal-independent charge injection. Based on this scheme, different topologies for the memory cell are discussed. To verify the theoretical concepts developed, a third-order elliptic low-pass SI filter is implemented in a 0.25-/spl mu/m digital CMOS process. The filter nominally operates with a clock frequency of 10 MHz, cutoff frequency of 1 MHz, and a power supply of 2.3 V, while consuming 29 mW of power and processing input signals as large as 600-/spl mu/A peak differential. The low-charge injection nature of the circuit is reflected in its low total harmonic distortion of -59 dB for a 0.3-MHz signal with a modulation index of 0.5.

The paper provides a new approach to an efficient reduction of switching noise in switched-current (SI) circuits. This approach makes use of a noise-free current-mode switch that can cut itself off to shield a circuit node, at which the voltage needs to be preserved precisely, from switching noise. With this approach, a reduction rate of more than 90% can be achieved. This approach can be very easily implemented. It does not require any special fabrication process, area-consuming components, matching devices, or complex clocks. This work can lead to a significant improvement of the operation quality of SI circuits without sacrificing speed and power dissipation.

This paper describes a theoretical study of the main errors in switched-current (SI) cells, such as conductance ratio error, settling time error and charge injection error, and their influence on the output/input transfert characteristic. First, our interest is focused on the study each error mechanism and its effect on the SI memory cell. After that, we studied the influence of their cumulative effect. Finally, we detailed the effect of cumulative error on the integrator level. The most significant non-idealities of SI cell are identified and their cumulative effect on SI cell and SI integrator transfert characteristic are analytically demonstrated.

This paper introduces a Switched-current Analysis Program (SIAP) that can perform both transient and frequency domain analysis of switched-current (SI) circuits. The program uses sparse matrices to reduce storage requirements and computation time. Transient analysis is performed using the large signal MOSFET model and the frequency domain analysis uses the small signal MOSFET model that includes all parasitic capacitance. All devices are modeled in a manner comparable with HSPICE and include almost all nonidealities, such as nonideal switches, clock feedthrough, channel-length modulation and transistor parasitic capacitors. Multiple inputs are allowed in both the transient and frequency domain analysis, thus differential circuits can be easily analyzed.

: The investigations were conducted to establish the feasibility of incorporating a high voltage switch within the electrical header of an exploding bridgewire initiator and to determine the electrical capabilities of the voltage switch to meet missile safety and functional requirements. Two types of high voltage switches were designed, developed, and fabricated within the electrical header of an EBW initiator. The electrical capabilities of these voltage switches were evaluated under various environmental conditions. Their conformance to the required design parameters established the feasibility of including a high voltage switch within the electrical header. Various stand-off gap switch (SOGS) and stand-off voltage switch (SOVS) engineering models were studied in the feasibility investigation. Fifty prototype SOVS initiator headers of the final design configuration were fabricated. These units, designed for a coaxial input, utilize the electrical voltage breakdown characteristics of an aluminum-oxide coating for the voltage switch.

The possibility of using the switched-voltage (SV) technique for a CMOS standard process is explored. Simple blocks which realize signal inversion, summation and delay, based on voltage inverters, are proposed. SV circuits are modeled using SPICE and compared to their switched-current (SI) counterparts based on current mirrors. These simulations show that the error, caused by the clock feed-through effect is smaller in the SV stage than in the SI one.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

We study voltage-induced conductance changes of Pb, Au, Al, and Cu atomic contacts. The experiments are performed in vacuum at low temperature using mechanically controllable break junctions. We determine switching histograms, i.e., distribution functions of switching voltages and switching currents, as a function of the conductance. We observe a clear material dependence: Au reveals the highest and almost conductance-independent switching voltage, while Al has the lowest with a pronounced dependence on the conductance. The theoretical study uses density functional theory and a generalized Langevin equation considering the pumping of particular phonon modes. We identify a runaway voltage as the threshold at which the pumping destabilizes the atomic arrangement. We find qualitative agreement between the average switching voltage and the runaway voltage regarding the material and conductance dependence and contact-to-contact variation of the average characteristic voltages, suggesting that the phonon pumping is a relevant mechanism driving the rearrangements in the experimental contacts.

Low switching losses, high frequency operation enabling high power density, efficiency, and reduced voltage stress are the bench-marking parameters for active clamp forward converters. Synchronous rectifiers further aid the cause of loss reduction by lowering the secondary side losses. However, these inherently come with a value of high parasitic capacitances $(C_{p})$, which play an important role in the behaviour of these topologies. Their interaction with resonant inductor $(L_{r})$ in the primary side leads to oscillations in the resonant inductor current and primary switch voltages - an effect, which gets increasingly pronounced with higher parasitic capacitance values. It also results in high switch voltage stress, thereby undermining the benefits of switch voltage clamping. This paper analyzes the effects and discusses the change in topological modes with both low and high parasitic capacitance. This paper also analyzes the changes in the switch voltage stress with the addition of L<inf>r</inf> and discusses the design criterion to arrive at its upper limit based on the maximum allowable voltage stress across the main switch.

In this paper, we present the results of case studies conducted in three software companies in order to identify the improvement targets in their test processes. The test processes were modeled using the LAPPI (A Light-weight Technique to Practical Process Modeling and Improvement Target Identification) technique. Identifying improvement targets quickly and in a cost-effective way is important to maximize the value of SPI (Software Process Improvement) initiatives. The most significant problems identified in this study were the low level of unit testing, unknown repercussions of code changes, and missing exit criteria for testing. These findings support the results of earlier studies. Further, a less reported problem was identified. It appears that software companies find it difficult to integrate test automation with their manual test processes. Making the recurring test related problems known among the software industry helps to justify the need for test process improvement and standardization of test processes.

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Ramped-current and ramped-voltage current–voltage (I–V) measurements were carried out to investigate the conduction in ultrathin SiO2 films after breakdown, and all the I–V characteristics were plotted on a log–log scale to examine the power law behavior. In most cases, the conduction was stable, and the two measurements yielded identical I–V characteristics. However, in some cases, two phenomena exhibiting instability, i.e., the current switching and voltage switching between two well-defined states, were observed in the ramped-voltage and ramped-current measurements, respectively. For both the stable conduction with a single conduction state and the unstable conduction which involved different states, a linear relationship was observed in the log–log scale I–V characteristics for each state, indicating that each state followed a power law. The conduction instability is explained by a model based on the percolation concept.

This paper presents the design and development of a 3.3 kV silicon carbide (SiC) based reverse voltage blocking half-bridge module for the first time. This low inductance module can build a single-phase or a three-phase current source inverter (CSI). The module comprises of a SiC-MOSFET (3.3 kV/50 A die) and a SiC-MPS diode (3.3 kV/50 A die) to form a 3.3 kV SiC-based current switch in the half-bridge configuration. The static characterization of the current switch (CS) is performed, and a double pulse test circuit is used to verify the switching performance of the developed module. Additionally, the inverter efficiency is estimated for a 30 kW three-phase CSI for a motor drive application, using the obtained static and dynamic characterization results. The impact of the module inductances on the switch voltage and currents is discussed, thus illustrating the importance of a module-based design for CSI applications.

A new structure of metal/i-SiC/c-Si(n/sup +/-P) (MISS) bidirectional switching device is successfully developed for the first time. A thick sputtered SiC layer is used, instead of the thin insulating layer in the conventional MISS structure. Due to the wide band gap of the silicon carbide (2.3 eV for /spl beta/-SiC), this bidirectional switching device possesses a high switching voltage, e.g. 134 V for the 3000 /spl Aring/ silicon carbide thickness. The corresponding switching currents and holding current are 0.16 mA and 1.1 mA, respectively. Experimental results show the switching voltage V/sub s/ increases with increasing intrinsic silicon carbide thickness. This study indicates that the silicon carbide bidirectional switching device is a promising element for high-voltage switching applications.