CAD tools for microprocessor design in the deep submicron era

Coupling Of Synthesis And Layout: Challenges And Solutions

In this paper we propose a distributed system LSI design environment where both LSI designers and CAD tool developers/ engineering can collaboratively work for higher performance designs. What we propose is a framework where not only design issues but also CAD tool related problems can be simultaneously taken care of by both designers and CAD engineers. Traditional design tools and flows are assuming to use CAD tools which have been fully developed and cannot be modified or enhanced when designing LSI chips. In order to use the most advanced LSI technology, however, it is essential to use the most advanced CAD tools which may not be fully debugged and tuned yet. This means that CAD tools must be enhanced when designing a new advanced LSI chip. Also we briefly discuss about implementation issues of the proposal on top of Croquet type distributed environments by showing a debugging process of hardware logic designs. We define consistency conditions on the use of CAD tools for the target LSI design flows including interface issues among various CAD tools used in the design flow and analyze them with a method similar to model checking type approaches used in formal analysis. We define virtual shared screens for both LSI designers and CAD developers/engineers collaboration and monitors activities on them, which will be the base of our model checking type analysis. We examine various issues including interface checking among CAD tools, interface checking among design blocks, and tool performance enhancement/ design modifications.

Deep sub-micron chip development

The transient sensitive trigger (TST) was used to improve the RC delay time of the long interconnection in deep sub-micron process. The conventional TST circuit has a threshold voltage drop during transitions which results in a longer delay time. In this work, modified techniques are proposed to improve the drawbacks of the conventional TST. The new versions have 45-74% delay improvement compared to the conventional TST, simulated using a 0.25 /spl mu/m CMOS process. The proposed circuits can be applied to the receiving of long interconnection signals for high-speed VLSI applications.

TCAD has contributed to processldevice design and prediction of the device performances for decades. This role is still very important in very deep submicron process; however, new aspect in the semiconductor industry has arisen. Interconnect issue becomes more critical in SoC timing closure. ITRS roadmap predicts future of processldevices and interconnects, which lead to a standardized process and device. TCAD seems to be requested to contribute in the new situation of SoC era. The panel addresses topics such as: What is the new role of TCAD in SoC era? How TCAD can contribute towards the ultimate-solution in timing closure problem. How to attack SI(Signa1 Integrity) Physical Design by TCAD. Can TCAD make innovation on Process & Device, which changes the ITRS2001?

Interconnect scaling to deep submicron processes presents many challenges to today's CAD flows. A recent analysis by Sylvester and Keutzer examined the behavior of average length wires under scaling, and controversially concluded that current CAD tools are adequate for future module-level designs. In our work, we show that average length wire scaling is sensitive to the technology assumptions, although the change in their behavior is small under all reasonable scaling assumptions. However, examining only average length wires is optimistic, since long wires are the ones that primarily cause CAD tool exceptions. In a module of fixed complexity, under both optimistic and pessimistic scaling assumptions, the number of long wires will increase slowly with scaling. More importantly, as the overall die capacity grows exponentially, the number of modules and thus the total number of wires in a design, will also increase exponentially. Thus, if the design team size and per-designer workload is to remain relatively constant, future CAD tools will need to handle long wires much better than current tools to reduce the percentage of wires that require designer intervention.

With shrinking device size in deep submicron process, many non-ideal effects impact circuit performances critically. Since those effects are often not considered in traditional analog synthesis tools, several sizing-layout iterations are still required to reach the desired performance and design yield. In this paper, an integrated analog synthesis tool is presented to consider the process variation, layout effects, and final layout generation simultaneously, with a user-friendly GUI to help users complete the design flow efficiently. With the consideration of those non-ideal effects in early design stages, blind design margins and time-consuming re-design cycles can be avoided in the proposed tool, which significantly reduces the design overhead. As shown in the experimental results, this analog synthesis tool is able to generate the required circuits in seconds and effectively guarantees the post-layout performance and design yield with less hardware cost.

Digital single event transients induced in combinatorial logic are quickly becoming a significant error source as circuit feature sizes shrink and digital circuits operate faster. In this paper, we are able to compare the combinatorial logic error rate to the sequential logic error rate in both heavy ion and proton environments in a simple digital circuit created in a 0.18 /spl mu/m CMOS technology. We are able to do this by comparing data from two unique test chips.

Due to the development of high performance portable applications associated to the high-density integration allowed by deep submicron processes, circuit optimization under delay constraints has emerged as a critical issue for VLSI designers. The objective of this work is to avoid the use of random mathematical methods (very CPU time expensive), by defining simple, fast and deterministic indicators allowing easy and fast implementation of circuits at the required speed. We propose to extend the method of equal sensitivity, previously developed for combinatorial paths [1], to circuit sizing in order to solve the circuit convergence branch problem. We propose a coefficient based approach to solve the divergence branch problem. Validation is given by comparing with an industrial tool the performance of different benchmarks implemented in a standard 180nm CMOS process.

Leakage current is the main source of power dissipation in low-frequency digital circuits implemented in deep submicron processes. This contribution introduces a novel active-mode leakage reduction technique for ultra-low-power (ULP) low-frequency applications. It is based on the ULP CMOS logic style achieving negative-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> self-biasing ULP logic gates have static current reduced by several orders of magnitude. For a commercial 0.13-μm technology, power consumption of ULP gates at low frequencies is lower than standard CMOS counterparts even considering high-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> devices, subthreshold operation and reverse body biasing. ULP gates are shown to be very stable against process, voltage and temperature variations.

The ring oscillator (RO) is applied to many modern circuits given its simplicity, low-area-cost, low-power. However, the temperature-drifting propagation delay of logic gates makes the RO a difficult solution for frequency reference design in deep submicron process. This work presents the design and implementation of a temperature self-compensation architecture based on a balanced hybrid ring oscillator (BHRO) for precise temperature compensation and clock-on-chip applications. The proposed BHRO is formed by both PTAT (proportional to the absolute temperature) and CTAT (complementary to absolute temperature) delay cells to implements RO-internal compensation. The features include temperature-self-compensation, process insensitive and low-area-cost. Four different test chips are fabricated in the 0.13μm CMOS process. The measurement result exhibits two performance-friendly BHRO architectures with a best temperature coefficient of 31 ppm/C over -55 to 80 , which is among the lowest to our best knowledge. The output compensated frequency is verified to be adjustable varying from 6.95 MHz to 26.5MHz, which are the highest as we have known.

A reflowed borophosphosilicate glass (BPSG) film having surface ridges is polished with a colloidal silica slurry, and the ridge width effect on the planarization rate or the efficiency is investigated. The planarization rate decreases drastically with increasing ridge width; thereby it is impossible to effectively remove the wide ridges corresponding to the stacked-type memory cell array areas in a dynamic random access memory (DRAM) device. Then, a nitride-masked polishing (NMP) technique is developed in which the BPSG surface except for the ridge areas, is covered with a Si3N4 film and the ridges are selectively polished away. A BPSG film on a DRAM with stacked-type capacitors is planarized by NMP to insure a tight focus margin for photolithography below deep submicron processes.

The advancement of very large scale integration (VLSI) technologies has been following Moore’s law for the past several decades: the number of transistors on an integrated circuit is doubling every two years [4] and the channel length is scaling at the rate of 0.7/3years [68, 41]. It was not long ago when VLSI design marched into the realm of Deep Submicron (DSM) processes, where the minimum feature size is well below 1µm. These advanced processes enable designers to implement faster, bigger and more complex designs. With the increase in complexity, System on Chip (SoC), Network on Chip (NoC) and Chip-level Multiprocessing (CMP) based products are now readily available commercially.

Most CAD tools cater to digital IC design and enable an entire system to be simulated at a behavioral level. When the designer is satisfied with a particular architecture, a netlist can be automatically synthesized and laid out. This is in sharp contrast to tools for analog IC design; no single platform exists for the automated design of an RF transceiver. This paper describes the design flow and CAD tools used in the design, simulation, and layout of a single-chip 900 MHz CMOS wireless transceiver. Large sections of this chip were simulated and laid-out using tools meant for digital circuit design. These tools did not have features to assist in analog layout and simulation, but allowed us to take advantage of the extensive silicon generators developed by our digital design group. We were forced to improvise when the existing tools could not meet our needs, or when no tool existed for the task. With this design flow, we produced a chip with measured results on first silicon very close to simulation.

The trend in design and manufacturing of very large-scale integrated (VLSI) circuits is towards smaller devices on increasing wafer dimensions. VLSI is the inter-disciplinary science of the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI design can reduce the area of the circuit, making it less expensive and requiring less power.The book gives an understanding of the underlying principles of the subject. It not only focuses on circuit design process obeying VLSI rules but also on technological aspects of prototyping and fabrication. All the clocking processes, interconnects, and circuits of CMOS are explained in this book in an understandable format. The book provides contents on VLSI Physical Design Automation, Design of VLSI Devices and also its Impact on Physical Design.The book is intended as a reference book for senior undergraduate, first-year post graduate students, researchers as well as academicians in VLSI design, electronics & electrical engineering, and materials science. The basics and applications of VLSI design from STA, PDA and VLSI Testing along with FPGA based Prototyping are covered in a comprehensive manner.The latest technology used in VLSI design is discussed along with the available tools for FPGA prototyping as well as ASIC design. Each unit contains technical questions with solutions at the end.Technical topics discussed in the book include: • Static Timing Analysis• CMOS Layout and Design rules• Physical Design Automation• Testing of VLSI Circuits• Software tools for Frontend and Backend design.