Design and Analysis of VLSI Circuits Based on Directed Acyclic Graphs

Due to high packaging density of components, power is increasingly becoming the bottleneck for the design of high performance VLSI circuits. It is essential to analyze how the various components of power are likely to scale in the future, thereby identifying the key problematic areas. This is an important fact because the conventional design, analysis, and synthesis of VLSI circuits are based on the assumption that gates are the main sources of on-chip power consumption. While most analysis focus on the timing aspects of interconnects, power consumption is also important. In this paper, the power distribution estimation of interconnects is studied using a reduced-order model. The relation between power consumption and the poles and residues of a transfer function is derived, and an appropriate driver model is developed, allowing power consumption to be computed efficiently. At higher frequency of operations, of the order of few GHz, the interconnect is to be analyzed with a distributed RLCG model. Because at very high frequency, the dielectric material deviates from it's ideal nature. This gives rise to the shunt conductance matrices. In this paper we have considered the high frequency effects and modeled the interconnect as distributed RLCG segments to compute the interconnect power dissipation. The results obtained from SPICE simulation justify the accuracy of our model.

With the ever-increasing complexity, circuit verification at the full-chip level is a major bottleneck in the design of VLSI circuits. This paper presents procedures that verify a given CMOS/BiCMOS VLSI circuit for its compliance to a set of pre-defined rules or design styles. Predefined rules range from simple connectivity and sizing rules to specific circuit topologies ensuring acceptable circuit speed, reliability, and signal integrity. Our compliance checks operate on transistor-level circuit netlists, which may contain back-annotated parasitics. The procedures and rules have been implemented in a checker called Elecdra. VLSI circuits with over 3 million devices have been successfully verified by Elecdra at the full-chip level.

This paper deals with the optimal design of different VLSI circuits, namely, the CMOS voltage reference circuit and the CMOS ring oscillator (RO). The optimization technique used here is the multiobjective differential evolution algorithm (MDEA). All the circuits are designed for 90 nm technology. The main objective of the CMOS voltage reference circuit is to minimize the voltage variation at the output. The targeted value of the reference voltage is 550 mV. A CMOS ring oscillator (RO) is designed depending on the performance parameters such as power consumption and phase noise. The optimal transistor sizing of each circuit is obtained from MDEA. Each circuit is implemented in SPICE by taking the optimal dimensions of the transistors, and the performance parameters are achieved. The designed voltage reference circuit achieves a reference voltage of 550 mV with 600 nW power dissipation. The reference voltage variation of 8.18% is observed due to temperature variation from −40°C to + 125°C. The MDEA-based optimal design of RO oscillates at 2.001 GHz frequency, has a phase noise of −87 dBc/Hz at 1 MHz offset frequency, and consumes 71 μW power. This work mainly aims to optimize the MOS transistors’ sizes using MDEA for better circuit performance parameters. SPICE simulation has been carried out by using the optimal values of MOS transistor sizes to exhibit the performance parameters of the circuit. Simulation results establish that design specifications are closely met. SPICE results show that MDEA is a better technique for the optimal design of the above-mentioned VLSI circuits.

In this paper the analysis and design of next-generation VLSI circuits using accurate electromagnetics-based models result in numerical problems of very large scale is presented. Typically, the solution of a problem with N parameters requires at least O(N) computation. With next generation VLSI circuits, however, even O(N) is prohibitively high since N is very large. The method that partially addresses this issue was developed for full-wave modeling of large-scale interconnect structures. In this method, a number of seeds (a seed has a unique cross section) are first recognized from an interconnect structure. In each seed, the original wave propagation problem is represented as a generalized eigenvalue problem. The complexity of solving 3D interconnects of O(N) is then overcome by seeking the solution of a few 2D seeds, which is then post-processed to obtain the solution of the original 3D problem through the development of an on-chip mode-matching technique. The computational bottleneck is the solution of a generalized eigenvalue problem. Efficient algorithms such as ARPACK [2] still require O(M2) storage and operations due to a dense matrix-vector multiplication. We present an algorithm that provides a solution to the generalized eigenvalue problem with O(M) complexity, thus paving the way for the full-wave simulation of next generation VLSI circuits.

Coupling Of Synthesis And Layout: Challenges And Solutions

The development of an MOS transistor charge and capacitance model for the analysis and design of VLSI circuits is described. The total stored charge in each of the gate, bulk, and channel regions is obtained by integrating the distributed charge densities over the thin-oxide area. Charge conservation is guaranteed in this model by using the terminal charges as the state variables. The capacitance expressions have the nonreciprocal property. Partition of channel charge into the drain and source components is 40/60 in the saturation region. In the triode region, this partition changes asymptotically to 50/50 as the gate voltage increases. The carrier-velocity saturation effect is incorporated through both the modification of channel quasi-Fermi level and the determination of drain saturation voltage. Implementation of the model in the SPICE circuit simulator has been achieved. Modeled results compare well with experimental data for transistors with channel lengths as small as 0.75 mu m.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The papers in this special section were presented at the 29th Symposium on VLSI Circuits, held on June 16–19, 2015 at the Rihga Royal Hotel Kyoto, Japan. Papers presented covered a broad range of topics important to VLSI circuit and system designers, including topics also important to integrated circuit technology developers.

This book explains the application of recent advances in computational intelligence algorithms, design methodologies, and synthesis techniques to the design of integrated circuits and systems. It highlights new biasing and sizing approaches and optimization techniques and their application to the design of high-performance digital, VLSI, radio-frequency, and mixed-signal circuits and systems. This first of two related volumes addresses the design of analog and mixed-signal (AMS) and radio-frequency (RF) circuits, with 17 chapters grouped into parts on analog and mixed-signal applications, and radio-frequency design. It will be of interest to practitioners and researchers in computer science and electronics engineering engaged with the design of electronic circuits.

Capacitance extraction for interconnect parasitics modeling is the basis of accurate circuit simulation and physical verification for quality integrated circuit (IC) design. Due to its scalability and reliability, the floating random walk (FRW) based solver has been widely used for the capacitance extraction. In this paper, the recently developed techniques on distributed parallel FRW solver and for handling complex floating metals are presented. With them, the efficiency and accuracy of capacitance extraction/simulation for very large-scale integration (VLSI) circuit design are remarkably improved.

This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully designed and verified using the proposed design tool. It is also shown in this paper that, the design results obtained from the proposed algorithm in MATLAB, have a very good agreement with the obtained circuit simulation results in HSPICE.

Computer-Aided Design (CAD) of microelectronic circuits is concerned with the development of computer programs for the automated design and manufacture of integrated electronic systems, with emphasis today on the design and implementation of Very Large Scale Integrated (VLSI) circuits. Automated VLSI design is referred to as VLSI synthesis. Synthesis of VLSI circuits involves transforming a specification of circuit behavior into a mask-level layout which can be fabricated using VLSI manufacturing processes, usually via a number of levels of representation between abstract behavior and mask-level layout. Optimization strategies, both manual and automatic, are vital in VLSI synthesis in order to meet required specifications. However, the optimization problems encountered in VLSI synthesis are typically non-deterministic polynomial-time (NP)-complete or NP-hard [35]. Therefore, solutions to the optimization problems incorporate heuristic strategies, the development of which requires a thorough understanding of the problem at hand. Thus, optimization-based VLSI synthesis has evolved into a rich and exciting area of research.KeywordsSystolic ArrayVery Large Scale IntegrateState EncodeSequential CircuitPrime ImplicantsThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Spike Timing Dependent Plasticity (STDP) is a time-based synaptic plasticity rule that has generated significant interest in the area of neuromorphic engineering and Very Large Scale Integration (VLSI) circuit design. During the last decade, STDP and STDP-like learning mechanisms have shown promising solutions for various real world applications, ranging from pattern recognition to robotics. This paper presents a novel analog VLSI model for STDP that possesses advantages compared to previously published VLSI STDP designs. The presented STDP circuit is capable of reproducing the outcomes of several well known experiments using various plasticity rules inducing STDP protocols that utilise pairs, triplets, and quadruplets of spike patterns. When the circuit is compared to state-of-the-art VLSI STDP circuits, it shows a compact and symmetric design that makes the proposed circuit a powerful component for use in designing STDP or time-based Hebbian learning experiments and applications.

CMOS is a popular technology today for very large scale integrated (VLSI) circuits. But, conventional functional testing cannot guarantee the detection of some defects. Built-in current testing has been suggested to enhance the defect coverage. In this paper, the authors present a high-speed built-in current sensing (BICS) circuit design. An experimental CMOS VLSI chip containing BICS is described. The power bus current of an 8*8 parallel multiplier is monitored. This BICS detects all implanted short circuit defects and some open circuit defects at a clock speed of 30 MHz (limited by the test set up). SPICE3 simulations indicate a defect detection time of 2 ns. >

Representing finite state systems by means of finite state machines is a common approach in VLSI circuit design. BDD-based algorithms have made possible the manipulation of FSMs with very large state spaces; however, when the representation of the set of reachable states grows too much, the original FSM is no longer manageable as a whole, and it needs to be decomposed into smaller sub-machines. Structural analysis of the circuit from which the FSM has been extracted has shown to be very effective to determine good state variable partitions which induce FSM decomposition for logic synthesis and formal verification applications. In this paper we propose FSM analysis techniques based on connectivity and spectral characteristics of the state machine which take into account the mutual dependency of the state variables, but which are no longer dependent on the structure of the underlying circuit; therefore, they may be used in a context different from sequential logic optimization and FSM verification.

High-performance as well as user-friendly circuit simulators are powerful aids for power electronics engineers. This paper presents a new circuit analysis and design simulator named TAP-T (transient analysis program TOKUZO) mainly for power electronics use. It offers ATP/EMTP like or more convenient CAD environment. It is almost free from the numerical oscillation problems which annoy ATP/EMTP users. This feature attributes largely to TAP-T's reasonable counter-measures against switching logic conflicts. Two benchmark tests are carried out on circuits designated by IEE JAPAN to verify high accuracy and short computation time of TAP-T.