Design of broadband high-efficiency GaN power amplifiers

In this paper, a hybrid continuous inverse mode for designing broadband high-efficiency power amplifiers (PAs) is for the first time analyzed mathematically. The hybrid continuous inverse mode contains the classical continuous inverse Class-F mode, the continuous inverse F mode with maximally flat current waveforms and the inverse Class-B to Class-J continuum mode and so on, which provides alternative design space for realizing the broadband high-efficiency PAs. And a high-efficiency PA at the center frequency of 3.45 GHz is designed to verify this theory. Experimental results show that the implemented PA can output 10.5–16 W saturation power with drain efficiency (DE) over 70% from 3.2 to 3.7 GHz. Meanwhile, for a 5 MHz two-tone signal, drain efficiency of 40.3%–48% is measured with an average output power of 34–36.5 dBm at a two-tone carrier-to-intermodulation ratio (C/I) of 30 dBc.

This paper presents a method for bandwidth extension in high-efficiency power amplifier (PA) design. With a phase shift in voltage waveform of the continuous class-F mode, real part of harmonic impedance is generated to expand the impedance design space at the expense of little lossy of performance. The simulation and measurement, conducted on a broadband PA covering 1.9-3.1 GHz based on the proposed method, show a good agreement with the theory. Measured results show that the fabricated PA has a drain efficiency of 66.5%-75% when delivering 41-42.3 dBm output power with a gain of 11-12.7 dB. Under a 20-MHz LTE signal excitation at 2.6 GHz, the PA exhibits an adjacent channel leakage ratio of -36.5 dBc at an average output power of 35 dBm without linearization.

: A key component of microwave telecommunication systems is the power amplifier (PA). The design parameters of a communication system, such as link performance, power budget, and thermal design are typically driven by the power amplifier's linearity, output power, and efficiency. These design parameters of PA are the key to ensuring an efficient system because the PA is the most power-consuming circuit in the communication system. In an effort to have students involved in this research area, the International Microwave Symposium (IMS) sponsored by IEEE Microwave Theory and Technique Society (MTT-S) has introduced a High Efficiency Power Amplifier Design Competition. In this report, we present a 2.8-GHz, 5-W, highly efficient PA based on a wide bandgap gallium nitride (GaN) high electron mobility transistor (HEMT) device (CGH 40010f from CREE). The PA design was presented at the 2010 IMS Student Design Competition and achieved the competition goal of output power greater than 5 W with a measured power added efficiency (PAE) of 61% at 2.8 GHz.

Design of high-efficiency power amplifier (PA) is one of the key challenges to realize green radios, wherein digital predistortion (DPD) is deployed to reduce the PA’s power back-off and thus increase its power efficiency. As the bandwidth of the transmit signal increases, stringent requirements are posed on the DPD linearization performance with limited sampling rate and dynamic range for the analog-to-digital converter (ADC) in the DPD feedback channel. In this paper, under a fixed ADC sampling rate, novel DPD architecture is proposed to compensate for the PA nonlinearity with limited ADC dynamic range. In the feedback channel of the proposed architecture, an extra radio frequency (RF) cancellation chain is introduced to eliminate the linear component of the PA amplified signal, and thus the requirement on the ADC dynamic range can be significantly reduced. Subsequently, by accurately estimating the loop delay and attenuation of the cancellation chain, the baseband replica of the RF cancelling signal is recovered, and the original PA output signal is rebuilt to estimate the DPD coefficients. Finally, experiments show that for the long term evolution (LTE)-advanced signals, the proposed architecture can achieve an adjacent channel leakage ratio lower than −47.6 dBc, which outperforms the conventional DPD by about 3.4 dB, with the effective bits of the ADC being reduced by 4.4 and a power added efficiency of 43.8% with 7.3 dB power back-off being observed for a fabricated Doherty PA with 50-dBm saturation power.

A series of novel continuous inverse modes based on current element is proposed. The series of novel continuous inverse mode is extended by increasing the coefficient in the current equation of traditional inverse class F power amplifier (PA). The theoretical analysis shows that new current equation can provide a wide matching space for the design of broadband high efficiency PAs. To prove this theory, a wideband high efficiency PA is designed and fabricated. The experimental test results show that the drain efficiency is 65-78% in the 1.8-3G frequency range. The designed PA can obtain output power from 12.9 to 21 W and gain is from 10 to 13.3 dB in the interesting frequency range.

To meet the demands for higher efficiency and size, weight, power, and cost (SWaP-C), a high efficiency Power Amplifier (PA) design is discussed. The primary focus is on Class F and Inverse Class F PAs for increased efficiency in P, L, S, and X band applications. By incorporating innovative matching techniques at the second and third harmonics and including fast voltage switching circuits, efficiencies over 80% are achievable at a peak output power greater than 25 Watts. These technologies allow for a reduction in battery size and cooling requirements, while achieving state-of-the-art efficiencies.

This paper presents the design of a multi-octave power amplifier (PA) using extended class B to class J continuous mode. In a multi-octave PA, an overlapping exists between the higher harmonic frequencies of the lower octave and the fundamental frequency of the higher octave. Therefore, a PA mode with overlapping between fundamental and second harmonic impedances is suitable to design a multioctave PA. An extended class B to class J continuous mode consists of overlapping between fundamental and second harmonic impedances. However, the design of a multi-octave PA is not straightforward. The impedance selected in each octave is important to design a highly-efficiency multi-octave PA. Therefore, this paper presents a methodology to choose the appropriate load in each octave to design extended class B to class J continuous mode PA. This paper also presents a valid range of design variables for the transistor’s reliable operation. The proof of concept PA has been designed using 10 W Wolfspeed GaN HEMT CGH40010F. The designed PA operates from 0.75 to 2.75 GHz. The corresponding fractional bandwidth is 114.2%. The measured drain efficiency, power added efficiency, and output power are 60-73.6%, 53-67.8%, and 39.3-42.3 dBm, respectively. The measured carrier to third-order intermodulation distortion is better than -15 dBc when tested with a 20 MHz spacing two-tone signal.

Preface. About the Authors. Acknowledgments. 1 Power Amplifier Fundamentals. 1.1 Introduction. 1.2 Definition of Power Amplifier Parameters. 1.3 Distortion Parameters. 1.4 Power Match Condition. 1.5 Class of Operation. 1.6 Overview of Semiconductors for PAs. 1.7 Devices for PA. 1.8 Appendix: Demonstration of Useful Relationships. 1.9 References. 2 Power Amplifier Design. 2.1 Introduction. 2.2 Design Flow. 2.3 Simplified Approaches. 2.4 The Tuned Load Amplifier. 2.5 Sample Design of a Tuned Load PA. 2.6 References. 3 Nonlinear Analysis for Power Amplifiers. 3.1 Introduction. 3.2 Linear vs. Nonlinear Circuits. 3.3 Time Domain Integration. 3.4 Example. 3.5 Solution by Series Expansion. 3.6 The Volterra Series. 3.7 The Fourier Series. 3.8 The Harmonic Balance. 3.9 Envelope Analysis. 3.10 Spectral Balance. 3.11 Large Signal Stability Issue. 3.12 References. 4 Load Pull. 4.1 Introduction. 4.2 Passive Source/Load Pull Measurement Systems. 4.3 Active Source/Load Pull Measurement Systems. 4.4 Measurement Test-sets. 4.5 Advanced Load Pull Measurements. 4.6 Source/Load Pull Characterization. 4.7 Determination of Optimum Load Condition. 4.8 Appendix: Construction of Simplified Load Pull Contours through Linear Simulations. 4.9 References. 5 High Efficiency PA Design Theory. 5.1 Introduction. 5.2 Power Balance in a PA. 5.3 Ideal Approaches. 5.4 High Frequency Harmonic Tuning Approaches. 5.5 High Frequency Third Harmonic Tuned (Class F). 5.6 High Frequency Second Harmonic Tuned. 5.7 High Frequency Second and Third Harmonic Tuned. 5.8 Design by Harmonic Tuning. 5.9 Final Remarks. 5.10 References. 6 Switched Amplifiers. 6.1 Introduction. 6.2 The Ideal Class E Amplifier. 6.3 Class E Behavioural Analysis. 6.4 Low Frequency Class E Amplifier Design. 6.5 Class E Amplifier Design with 50# Duty-cycle. 6.6 Examples of High Frequency Class E Amplifiers. 6.7 Class E vs. Harmonic Tuned. 6.8 Class E Final Remarks. 6.9 Appendix: Demonstration of Useful Relationships. 6.10 References. 7 High Frequency Class F Power Amplifiers. 7.1 Introduction. 7.2 Class F Description Based on Voltage Wave-shaping. 7.3 High Frequency Class F Amplifiers. 7.4 Bias Level Selection. 7.5 Class F Output Matching Network Design. 7.6 Class F Design Examples. 7.7 References. 8 High Frequency Harmonic Tuned Power Amplifiers. 8.1 Introduction. 8.2 Theory of Harmonic Tuned PA Design. 8.3 Input Device Nonlinear Phenomena: Theoretical Analysis. 8.4 Input Device Nonlinear Phenomena: Experimental Results. 8.5 Output Device Nonlinear Phenomena. 8.6 Design of a Second HT Power Amplifier. 8.7 Design of a Second and Third HT Power Amplifier. 8.8 Example of 2nd HT GaN PA. 8.9 Final Remarks. 8.10 References. 9 High Linearity in Efficient Power Amplifiers. 9.1 Introduction. 9.2 Systems Classification. 9.3 Linearity Issue. 9.4 Bias Point Influence on IMD. 9.5 Harmonic Loading Effects on IMD. 9.6 Appendix: Volterra Analysis Example. 9.7 References. 10 Power Combining. 10.1 Introduction. 10.2 Device Scaling Properties. 10.3 Power Budget. 10.4 Power Combiner Classification. 10.5 The T-junction Power Divider. 10.6 Wilkinson Combiner. 10.7 The Quadrature (90 ) Hybrid. 10.8 The 180 Hybrid (Ring Coupler or Rat-race). 10.9 Bus-bar Combiner. 10.10 Other Planar Combiners. 10.11 Corporate Combiners. 10.12 Resonating Planar Combiners. 10.13 Graceful Degradation. 10.14 Matching Properties of Combined PAs. 10.15 Unbalance Issue in Hybrid Combiners. 10.16 Appendix: Basic Properties of Three-port Networks. 10.17 References. 11 The Doherty Power Amplifier. 11.1 Introduction. 11.2 Doherty's Idea. 11.3 The Classical Doherty Configuration. 11.4 The 'AB-C' Doherty Amplifier Analysis. 11.5 Power Splitter Sizing. 11.6 Evaluation of the Gain in a Doherty Amplifier. 11.7 Design Example. 11.8 Advanced Solutions. 11.9 References. Index.

This paper presents the design of a class-J 1.35-1.75 GHz 150 W Power Amplifier with bounded performance technique (BPT). The amplifier achieves 3-dB compression power higher than 150 W and 3-dB drain efficiency better than 70% over the band 1.35-1.75 GHz. This design demonstrates the effectiveness of BPT in the design of high-efficiency power amplifier.

High performance broadband distributed power amplifier (PA) design relies on the co-design of input signal distribution and non-isolated output combiner to take maximum advantage of the resulting load-pulling effects at both fundamental and higher harmonics. Due to the load-pulling and the need to consider higher harmonics, PA operation is not readily expressed analytically. In this work this is addressed by using a numerical linear multi-harmonic calculation method for rapid circuit evaluation and optimization. This linear approach targets good broadband performance without relying on nonlinear saturation effects. An initial investigation is performed to find suitable input network and output combiner topologies for a two-cell PA configuration. A demonstrator is then designed based on the findings, where a 3-dB hybrid coupler with an offset transmission line in one branch is used to produce a frequency dependent phase difference between transistor cells. Measuring the PA at 40-V supply and 1-dB compression the output power is in the 43–46 dBm range with corresponding efficiencies of 46–58% across 0.85–2.7 GHz, whereas saturated efficiencies are typically in the 60%-range. The simultaneous combination of high output power and high efficiency reported across 100% fractional bandwidth is state-of-the-art and clearly shows the merit of the proposed PA design approach.

Developments within modern nonlinear measurement systems offer an increasing degree of flexibility to the microwave power amplifier (PA) designer. The PA designer has historically been a driving factor in setting the development directions of new measurement systems, fueling the paradigm, that PA innovations largely push new measurement requirements. It would appear that measurement system manufacturers are now the ones pushing the technology envelope. This paper discusses current trends within modern nonlinear measurement systems to determine who is leading whom and whether the aforementioned paradigm is shifting.

This thesis researches the design of transceiver front-end RF amplifiers for Bluetooth applications in GPDK 45 nm CMOS technology. The target of the design was to minimize the transceiver's power consumption while achieving the best device operating performances. The design of a band-pass low noise amplifier (LNA) used for the receiver and the design of a power amplifier (PA) used for the transmitter were presented. Both amplifiers were designed in 45 nm CMOS technology with a DC supply voltage under 1.2 V to meet Bluetooth specifications at 2.45 GHz operating frequency. The LNA was designed to achieve a minimum small signal gain of at least 15 dB10 with a NF less than 2 dB10 and a reasonable input range for linearity at 1 mW operating power consumption. The PA was designed based on class E switching power amplifier configuration to achieve a minimum of 40% drain efficiency for 100 mW (Bluetooth Class 1) output power. Research on low power high performance Bluetooth device front-end RF amplifiers was conducted through studies of wireless communication modulation schemes, impedance matching networks, and trade-offs between performance parameters. In summation, this thesis searched for, explored, and analyzed possible methodologies that could be used to design RF CMOS amplifiers of Bluetooth applications.

This paper presents recent advances in the state-of-the-art of neural network modeling of microwave FET devices. Enhanced accuracy of the adaptive knowledge-based neural network (AKBNN) model is shown by comparing predicted load-pull performance of the device to measurements in an automated harmonic load-pull system. Test devices are a 1.2 mm HFET measured at 2.2 GHz, and a 4.8 mm pHEMT at 8.4 GHz. Modeled versus measured comparisons include power-added efficiency and output power under fundamental frequency and second and third harmonic frequency tuning. The effectiveness of this modeling approach for the design of high-efficiency power amplifiers operating in Class-E or Class-F modes is discussed.

Radio frequency (RF) power supplies are important equipment in the semiconductor manufacturing process, and class E power amplifiers are widely used in RF power supplies due to their low switching losses. However, under the influence of parasitic parameters of class E power amplifier, soft switching is difficult to achieve. In RF high power applications, RF drivers are also difficult to design. In this paper, a soft-switching optimization method and a switch input impedance measurement method are proposed. The cascade structure of class E power amplifier is realized, and the sinusoidal output of the previous class E power amplifier is used to drive the second-stage class E power amplifier. In order to verify the validity of the theory, a class E power amplifier experimental prototype is built, with an output power of 2kW and an efficiency of 80.19%.

This letter presents the design of a high-efficiency Class-F power amplifier in pseudomorphic high electron mobility transistor technology using a novel load-pull/source-pull simulation-based approach. The second harmonic input termination is shown to have a critical influence on performance, which is justified by the shape of the simulated waveforms. Experimental validation is carried out on a 2-GHz practical circuit using a medium-power packaged device. Two cases are compared both theoretically and experimentally: for the best and worst case second harmonic input terminations, 76% and 42% saturated power-added efficiency are measured, respectively. In addition, the worst case termination degrades the saturated C/I3 by 7.5dB.