Design of Network Adapter Compatible OCP for High-Throughput NOC

System on Chip (SoC) design in the forthcoming billion-transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks. The success of this approach depends on the seamless integration of cores like processors, memories, UARTs, etc. Some of the main problems in future SoC designs arise from non scalable global wire delays, failure to achieve global synchronization, errors due to signal integrity issues and difficulties associated with non scalable bus-based functional interconnects. These problems can be addressed by using a network-centric approach to design SoCs, where instead of global wiring, IP blocks are integrated using a switch-based on-chip interconnection network. One of the major concerns with interconnection networks is throughput degradation due to idle physical channels. By introducing the concept of virtual channels in an on-chip interconnection network, the overall throughput of the SoC can be improved. To achieve this throughput improvement, extra silicon area is required but the overall area consumed by the switches can be made to amount to a very small portion of a billion transistor SoC.

With continued Moore's law scaling, multicore-based architectures are becoming the de facto design paradigm for achieving low-cost and performance/power-efficient processing systems through effective exploitation of available parallelism in software and hardware. A crucial subsystem within multicores is the on-chip interconnection network that orchestrates high-bandwidth, low-latency, and low-power communication of data. Much previous work has focused on improving the design of on-chip networks but without more fully taking into consideration the on-chip communication behavior of application workloads that can be exploited by the network design. A significant portion of this paper analyzes and models on-chip network traffic characteristics of representative application workloads. Leveraged by this, the notion of globally coordinated on-chip networks is proposed in which application communication behavior-captured by traffic profiling-is utilized in the design and configuration of on-chip networks so as to support prevailing traffic flows well, in a globally coordinated manner. This is applied to the design of a hybrid network consisting of a mesh augmented with configurable multidrop (bus-like) spanning channels that serve as express paths for traffic flows benefiting from them, according to the characterized traffic profile. Evaluations reveal that network latency and energy consumption for a 64-core system running OpenMP benchmarks can be improved on average by 15 and 27 percent, respectively, with globally coordinated on-chip networks.

The continuous improving of semiconductor technology integrates more processors into a single chip. While integrate multiple processors into a chip, the interconnection network of among the cores become a dominant performance bottleneck. Accordingly, this paper provides a new on-chip interconnection network, called Self Similar Cubic (SSC), for many-core architectures. By cooperating with proposed linking mechanism, routing algorithm, and switching architectures, SSC has better scalability, on-chip fabrication possibility, and high communication performance, than conventional on-chip networks, such as Mesh, and Hypercube. In this paper, the comparison of performance and area cost are proposed. The analysis results reveal that SSC can provide higher throughput and lower area cost than other on-chip networks. The performance per area cost of SSC is five times better than that of Mesh.

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Presents a paradigm that combines the speed of single address spaces with the traditional protection mechanisms found in multiple address space systems such as UNIX. Multiple address spaces are common today for providing safety and security in operating systems. A process in one address space cannot corrupt or compromise memory locations an another process's address space. However, inter-process communication is slow because it is expensive to context switch between address spaces. Single address space systems provide a solution to the problem of slow context switches. In a single address space system, which is typically implemented in a 64-bit address space, all processes shape a common address space. Hence, the need to move between address spaces during inter-process communication is avoided. It is our position that it is not strictly necessary to use a single address space in order to achieve fast inter-process communication. >

Increasing the number of virtual channels can improve the throughput in an on-chip interconnection network. High throughput butterfly fat tree (HTBFT) architecture to achieve high performance networks on chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to butterfly fat tree switch.

Distributed memory parallel machines are increasingly being used by the scientific community to provide computational power for solving problems. Building a distributed memory parallel machine offers a tremendous advantage in terms of cost and scalability over building a shared memory parallel machine. Unfortunately, distributed memory machines are much more difficult to program, mainly due to the lack of a single global address space. Communication between processors in a distributed memory machine is accomplished by message passing. The time cost for acquiring data from another processor's memory is significantly greater than the time cost of acquiring data from local memory. To assist the programmer in using a distributed memory machine, compilers have been developed which alleviate the need for the programmer to manage the lack of a global address space. These compilers will generate semantically correct code containing communication routines to produce a logically shared memory machine on a physically distributed memory machine. However, the runtime performance of the code emitted from some of these compilers can be further improved. This thesis is primarily concerned with advanced compilation techniques which will provide better runtime performance of programs written in imperative languages for regular scientific programs. The optimization of communication generation for distributed memory machines is used to produce this result. We look at two "state of the art" compilation systems and find that improvement in the communication code generated by these compilers is still possible. We have simplified existing descriptions of the various formalisms found in these compilers, while still providing enough formalism to study the problems in depth. We have extended some existing optimization techniques by enhancing the elimination of masks, by extending the notion of relaxing the owner computes rule, by extending the notion of replicating computation, and by extending the notion of replicating data. This thesis has discussed a novel technique to split loops so that they do not contain any guarded statements. Finally, we have suggested avenues for future research, as it is clear from this thesis that more work is required before compilation systems for distributed memory parallel machines will be widely used for general purpose computing.

Adaptive error correction in Orthogonal Latin Square Codes for low-power, resilient on-chip interconnection network

An adaptive networking method based on LoRa(Long Range) technology is proposed. The data transmission of wireless sensor networks widely used in the Internet of things is studied. A star network composed of Lora wireless transmission technology is designed to build an adaptive data transmission network. The design process of network topology, hardware and adaptive networking method of adaptive networking are introduced. Aiming at solving the problems of limited node capacity, adjacent frequency interference, and unreasonable channel resource allocation in the LoRa network, an adaptive frequency hopping mechanism is used for networking. The system uses I. MX6ULL as the main control and integrates 8 LoRa modules at the same time, which greatly improves the node capacity of the gateway. The server can realize real-time viewing and monitoring of node equipment, and real-time evaluation of channel communication quality.

Multi-Processor Systems-on-Chip (MPSoCs) are increasingly popular in embedded systems, but also on high performance systems. In such systems, the data bandwidth requirements keeps increasing as the number of processing elements increases. Therefore, a Network-on-Chip (NoCs) communication architecture use to be preferred than a communication based on shared buses, because it provides higher communication performance. The probability of failure increases in this systems, due to these great advances in integration scales and the increasing number of components on chip. Therefore Fault Tolerance will become a key aspect on designing the near future VLSI SoC, and especially on their interconnection Network on Chip (NoC). This paper focuses on describe the particular aspects of NoCs, and the proposed fault-tolerant strategies for NoCs.

Robust adaptive neural network control and backstepping design are considered. An adaptive neural network controller is established for a uncertain nonlinear output feedback system. The controller regulates the output to a neighborhood of origin by properly choosing design parameters, and keeps all signals of the closed-loop bounded.

Data parallel languages designed for distributed memory computing environments provide a single global address space to the programmer. The mapping from this global address space to the distributed local address space is performed by a compiler, which does this mapping based on the array distribution format. Thus, each array in a data parallel language program has its own distribution format. The Reshape function changes the array distribution format as well as the array shape. However, the changed distribution format cannot be represented by any distribution format supported in current languages. Because there is no suitable distribution format, it is necessary to change the reshaped distribution format to an existing distribution format, with heavy overhead due to the redistribution function. To eliminate the redistribution step in Reshape function, we have proposed a new distribution format, HIER-CYCLIC, which can represent the reshaped distribution format. We have also proposed a language syntax to use HIER-CYCLIC and a compiling mechanism. Finally, we performed an experiment on an IBM-SP2 machine using a shift function.

The stability of a hybrid AC-DC microgrid depends mainly upon the bidirectional interlinking converter (BIC), which is responsible for power transfer, power balance, voltage solidity, frequency and transients sanity. The varying generation from renewable resources, fluctuating loads, and bidirectional power flow from the utility grid, charging station, super-capacitor, and batteries produce various stability issues on hybrid microgrids, like net active-reactive power flow on the AC-bus, frequency oscillations, total harmonic distortion (THD), and voltage variations. Therefore, the control of BIC between AC and DC buses in grid-connected hybrid microgrid power systems is of great importance for the quality/smooth operation of power flow, power sharing and stability of the whole power system. In literature, various control schemes are suggested, like conventional droop control, communication-based control, model predictive control, etc., each addressing different stability issues of hybrid AC-DC microgrids. However, model dependence, single-point-failure (SPF), communication vulnerability, complex computations, and complicated multilayer structures motivated the authors to develop online adaptive neural network (NN) Q-learning-based full recurrent adaptive neurofuzzy nonlinear control paradigms for BIC in a grid-connected hybrid AC-DC microgrid. The proposed strategies successfully ensure the following: (i) frequency stabilization, (ii) THD reduction, (iii) voltage normalization and (iv) negligible net active-reactive power flow on the AC-bus. Three novel adaptive NN Q-learning-based full recurrent adaptive neurofuzzy nonlinear control paradigms are proposed for PQ-control of BIC in a grid-connected hybrid AC-DC microgrid. The control schemes are based on NN Q-learning and full recurrent adaptive neurofuzzy identifiers. Hybrid adaptive full recurrent Legendre wavelet-based Neural Network Q-learning-based full recurrent adaptive NeuroFuzzy control, Hybrid adaptive full recurrent Mexican hat wavelet-based Neural Network Q-learning-based full recurrent adaptive NeuroFuzzy control, and Hybrid adaptive full recurrent Morlet wavelet-based Neural Network Q-learning-based full recurrent adaptive NeuroFuzzy control are modeled and tested for the control of BIC. The controllers differ from each other, based on variants used in the antecedent part (Gaussian membership function and B-Spline membership function), and consequent part (Legendre wavelet, Mexican hat wavelet, and Morlet wavelet) of the full recurrent adaptive neurofuzzy identifiers. The performance of the proposed control schemes was validated for various quality and stability parameters, using a simulation testbench in MATLAB/Simulink. The simulation results were bench-marked against an aPID controller, and each proposed control scheme, for a simulation time of a complete solar day.

With the advent of the 64-bit microprocessor, the virtual address space supported by a workstation will be large enough to permit the use of a single shared address space spanning a network of workstations as the primary abstraction provided by a distributed operating system. In such a system, built upon a software distributed shared memory, the programmer has considerable flexibility when choosing a mechanism for interprocess communication. This flexibility permits the programmer to make a case-by-case choice between simplicity and performance when both goals are not simultaneously achievable. With the inclusion of mechanisms supporting protection and fault tolerance, it is believed that such a system can provide the advantages of conventional message-based distributed operating systems, in addition to several other benefits e.g. easy sharing of complex data structures between processes, transparent replication of server functions, and a uniform interface for all communication. >

We present a panorama picture on how to achieve end-to-end video over IP service under the communication environments, consisting of backbone networks, hybrid access networks, and the end users. The paper consists of three equally weighted subtopics which cover some novel thoughts in designing and implementing the video over IP system in the different areas, namely, a Synchronous Optical NETwork (SONET) network adapter for backbone connections, the joint source-channel multistream coding in hybrid access networks, and the content-based source coding in the transform domain. We propose to link the three different problems associated with the hybrid networks, which have different characteristics and design requirements, to improve the critical performances in various areas of video over IP systems. The goal is to deliver video over IP networks in more cost-effective and reliable manner. IP/ATM over SONET is currently a commonly used backbone technique. In the first part of this paper, we present a flexible design and implementation of a SONET network adapter to carry IP traffic via optical fiber. Unlike many conventional designs, our single-chip implementation supports different data rates (OC-3, OC-12, and OC-48), carries IP traffic directly over fiber, achieves more flexible for multivendor interoperability, and provides bandwidth efficient designs at the lower system latency. Hybrid access-networks via wireline or wireless connections are most likely needed for last-mile services. In the second part of this paper, we propose a joint source-channel multistream video coding scheme to combat the transmission errors under the harsh network conditions. On top of traditional error control techniques, the simulation results demonstrate that our multistream design outperform the conventional approaches by up to 5-7 dB under the harsh network conditions. To support our multistream video coding scheme, we need to access and manipulate video objects rather than the frame of pixels. In the third part of this paper, we focus on the coding of arbitrary shape video fully in the transform domain.