Design Recipes for FPGAs

Road network map is one of the datasets that are used in many different applications. Many smart cities have more than one Road Network map from different sources (government authorities, private enterprise, or volunteered). Be that as it may, there is a high chance of mismatches between road maps that represent the same area for different reasons. These reasons include: one of the datasets is not updated; datasets have different names for the same road; and so on. As a result, matching the roads in such datasets with each other is challenging. This paper introduces a framework that demonstrates methods of how two datasets for the same area can be matched to each other even though there are some data discrepancies. In addition, it gives an overview of each component of the framework and focuses mainly on the similarity measurements. These measurements are local divergence measurements and global divergence measurement. Local divergence measurements compare two roads from different datasets to each other to see if they are similar or not by deciding if these two roads have a similar shape as well as the same length. On the other hand, global divergence measurement is used in order to ensure that these two roads are similar in the real world, not different roads that happen to be beside each other having similar length and shape. This paper discusses several types of applications that could utilize this framework not only for matching different road maps and unify the information for smart cities usages but also data enrichment and being up-to-date.

We propose the use of deep neural networks (DNN) for solving the problem of inferring the position and relevant properties of lanes of urban roads with poor or absent horizontal signalization, in order to allow the operation of autonomous cars in such situations. We take a segmentation approach to the problem and use the Efficient Neural Network (ENet) DNN for segmenting LiDAR remission grid maps into road maps. We represent road maps using what we called road grid maps. Road grid maps are square matrixes and each element of these matrixes represents a small square region of real-world space. The value of each element is a code associated with the semantics of the road map. Our road grid maps contain all information about the roads' lanes required for building the Road Definition Data Files (RDDFs) that are necessary for the operation of our autonomous car, IARA (Intelligent Autonomous Robotic Automobile). We have built a dataset of tens of kilometers of manually marked road lanes and used part of it to train ENet to segment road grid maps from remission grid maps. After being trained, ENet achieved an average segmentation accuracy of 83.7%. We have tested the use of inferred road grid maps in the real world using IARA on a stretch of 3.7 km of urban roads and it has shown performance equivalent to that of the previous IARA's subsystem that uses a manually generated RDDF.

This paper analyzes the difficulties of steel template design. BIM information model was used for reference to set up a three-dimensional model. Structure safety, forming quality and construction convenience were fully considered. This paper takes Nanchang Chaoyang bridge as an example for the work of template design in each stage. By exploring the selection criteria of shaped structural steel template and establishing the corresponding calculation and design method, the implementation quality of the bridge tower was ensured. Research formed a template design system of template calculation and design. This system provided reference for other similar types of special structure template design.

The road map in this research proves that the universe emerged from SUSY. Proving that, we link between two different classes of SM, fermions, and bosons in supersymmetry with their properties in the Standard Model of particle physics. According to SM properties, the bosons have spin one, while fermions have spin 1/2. We suggest differentiating between bosons and fermions angular momentum in our real world with a supersymmetrical state. We presume that bosons and fermions in their supersymmetric environment will have akin graviton spin angular momentum 2, while their superpartners will have spin one. In addition to that, in the supersymmetric environment, the fermion, boson, and their counterparts experience CPT conservation. They enjoy eternity with "Gravitons." Once upon a time, the boson and fermion descended from a supersymmetric state down through string theories' dimensions and M-theory's branes, stabilizing and forming SM quarks and, therefore, everything in our real world

The design, implementation and comparison of Software-Defined Radio (SDR) based on GALS architectures were focused on. GALS port controllers, previously proposed for implementation in ASIC, have been redesigned for use in conventional FPGAs, eliminating the need for hard macros. A GALS architecture for SDR was proposed and validated, comprising a wrapper described in VHDL. In addition, some guidelines for its implementation in synchronous designs are shown. Whereas asynchronous wrappers were designed to be robust and to dispense timing verification, the verification effort is negligible, since the same test benches can be used for both designs. When compared with a synchronous design, a reduction of 39% in the dynamic consumption was obtained, what may be even greater if the idle clock periods are considered. We saw that for the same device, it is possible to earn 53% in the data flow (throughput), signifying that the radio is able to process a broader band, or that the cost of equipment can be reduced, once it is possible to adopt a cheaper FPGA version with lower performance.

The measure of map information has been one of the key issues in assessing cartographic quality and map generalization algorithms. It is also important for developing efficient approaches to transfer geospatial information. Road network is the most common linear object in real world. Approximately describe road network information will benefit road map generalization, navigation map production and urban planning. Most of current approaches focused on node diversities and supposed that all the edges are the same, which is inconsistent to real-life condition, and thus show limitations in measuring network information. As real-life traffic flow are directed and of different quantities, the original undirected vector road map was first converted to a directed topographic connectivity map. Then in consideration of preferential attachment in complex network study and rich-club phenomenon in social network, the from and to weights of each edge are assigned. The from weight of a given edge is defined as the connectivity of its end node to the sum of the connectivities of all the neighbors of the from nodes of the edge. After getting the from and to weights of each edge, edge information, node information and the whole network structure information entropies could be obtained based on information theory. The approach has been applied to several 1 square mile road network samples. Results show that information entropies based on edge diversities could successfully describe the structural differences of road networks. This approach is a complementarity to current map information measurements, and can be extended to measure other kinds of geographical objects.

This review summarizes some of the studies which have examined maps designed for navigation, such as road maps, tourist maps etc. Despite the importance of such maps, there has been little research into how people use them for way finding. The results from this research suggest that adults are not always very competent or confident in using maps in the real world. These results have implications both for studies of map design and for studies of how people navigate with maps. Future research is discussed and it is also suggested that school curricula should include education about the use of maps.

<div class="section abstract"><div class="htmlview paragraph">In the quest for reduced cost and shorter development times for fuel cell systems in industrial applications, two major issues arise. First, the electrochemical behavior of fuel cell systems is inherently difficult to predict. Second, testing fuel cell systems is resource intensive. These issues compound: Setting up an accurate model of a fuel cell system incurs long testing periods for model validation. Further, it does not guarantee acceptable results outside the tested range or for other membrane electrode assembly compositions.</div><div class="htmlview paragraph">To mitigate these two major issues an X in the Loop concept is proposed. Essentially, this is the direct integration of the test sample, here a single fuel cell, into the modelling environment of the whole system. In practice, two strategies with different levels of integration are defined.</div><div class="htmlview paragraph">The first strategy consists of initially deducing the operating parameters of the sample cell from the fuel cell system model. Then, setting them to the sample cell in the test bench. The response of the test sample is finally used to validate the designed system or update the parameters of the fuel cell model.</div><div class="htmlview paragraph">The second strategy is a step further towards the integration of the test sample into the model. Here, the core model of the fuel cell inside the fuel cell system model is completely replaced with the test sample, reducing the need for an accurate electrochemical model while improving the prediction of the behavior of the fuel cell system.</div><div class="htmlview paragraph">Compared to previously proposed testing concepts, here the balance of plants is directly integrated through a digital emulator, leading to a closer representation of the complete system. Furthermore, the test bench results are looped back to the model at run-time leading to a closer match between testing conditions and the real world as well a reduced impact of inaccuracies in the modelling of the fuel cell.</div><div class="htmlview paragraph">On the way to realizing this goal, an experimental test bench capable of showcasing working prototypes of the proposed operating strategies has been built.</div></div>

Consistency Evaluation of Landscape Design by a Decision Support System

This article introduces the EDCI template for human-centered design of e-services, which we developed in five iterations over five years. The template contains two dimensions (conceptual vs. real world and problem finding vs. solution development), yielding four phases of e-service design: 1) Explore, 2) Discover, 3) Concept and design, and 4) Implement and assess. Examples and reflections from applying EDCI in numerous action learning projects are provided. A single instantiation of the EDCI template to a specific e-service (environmental information management) is described. The primary contributions of this article are to introduce the EDCI e-service design template, demonstrate its usefulness in a learning context, illustrate its value within a specific real-world setting, and suggest how it might provide the early stages for a full e-service design theory.

Finite Element Analysis (FEA) and experimental techniques based laboratory courses are used in the mechanical engineering curriculum to equip students with numerical and experimental abilities to solve design problems. Review of mechanical engineering curricula in US universities found no definite structure for the numerical and experimental based laboratory courses to support the core courses. Also, the authors found that due to lack of knowledge about the application of finite element analysis and lack of collaboration of experimental laboratories in the universities and colleges, students are unable to apply theory, numerical tool and experiment, when it comes to complete product design. To be effective product development engineers, students have to know how to use these engineering tools effectively for various mechanical systems to design a product with perfection. This motivated the authors to develop, teach, and evaluate a laboratory course before the senior design project, where students will have hands on experience with product design. The application of theoretical, numerical and experimental techniques, and their interconnectedness, will also be addressed in this new course. The main three learning objectives of this course were: (1) the ability to apply physical and mathematical models to analyze or design the mechanical systems; (2) the ability to use numerical tools (e.g., FEA) and a fundamental understanding of the limitations of such tools; and (3) the ability to correlate the theoretical knowledge with FEA and experimental findings. Some of the issues observed from the previously taught FEA laboratory related course are: (1) students do not understand how to use FEA tools in practical design problems; (2) students are unable to relate the theory with numerical and experimental result; (3) students do not understand the importance of verification of numerical results; and (4) students with knowledge of a particular analysis background have problems setting up the product design requirements dealing with different analysis systems. To overcome these difficulties, the proposed course will select design problems related to heat, fluid, vibration, and fracture and examine the overall design process including preliminary design, material selection, manufacturing, analysis, and testing. Simulating the complexity of “real world” engineering will prepare students for their senior design projects. The main benefits of this course are: (1) application of theoretical, numerical, and experimental techniques to solve a design problem, and (2) hands on experience with design problems.

The use of the VHSIC Hardware Description Language (VHDL) has become very important to the simulation and implementation of digital systems in both industry and educational settings. Although VHDL is a powerful language with many capabilities, it has downfalls when considering the difficulty in learning the language as well as its limited capabilities for transitioning a design from initial concept to design entry and verification stages. This paper discusses techniques used to teach the VHDL design methodology to graduate students, as well as methods used to go through a complete design cycle from initial concept to final implementation. VHDL design techniques were developed using various projects and homework assignments, and different approaches to implementing the same function allowed direct comparisons of the speed and size of the designs. Different processes for taking a design from initial concept through chip implementation were discussed, and one example of the process is discussed here. A Finite Impulse Response (FIR) filter was conceptually designed using the MATLAB programming environment to determine adequate performance specifications such as filter size and quantization levels. The design was then written using a behavioral VHDL coding style, as well as a VHDL test bench to determine if the VHDL behavioral model provided the same results as the MATLAB model. After design synthesis of the behavioral description using Synopys tools, the same test bench was used again to verify the performance of the structural VHDL netlist with annotated place and route delay information provided from the Alters MaxPluslI tools. Final verification took place with at the board level using an Altera CPLD programmed with the FIR filter design.

Transmission electron microscopes have been built along with and guided by technological opportunities since the last five decades. Even though there are some “workhorse” type of microscopes, these instruments are still more or less built from the technological viewpoint and less from the viewpoint of ease of use in a wide range of applications. On the other hand, leading edge applications are the drivers for the development and the use of leading edge technology. The result then is a “race horse” which is of very limited benefit in “Real world”.During the last decade computers have been integrated to build microscope systems. in most cases, however, computers still have to deal with obsolete electron optical ray path designs and thus, have to be used more to overcome the problems of imperfect optics and bad design of ray paths than to provide optimized “Real world” capabilities.

The study focuses on efficient design and integration of Silicon Intellectual Properties (SIPs), as well as measurement of SIP physical signals to meet the following three objectives: 1. efficient design of master and slave wrappers by using the Unified Modeling Language (UML) model to describe System on Chip (SoC) bus behavior; 2. an SoC integration framework including master and slave SIP templates, memory controller, DMA and SoC bus analyzer to accelerate SoC integration; and 3. an SoC bus analyzer measuring physical hardware signals for bus protocol specification testing and thus to alleviate debugging from physical to system levels in the process of SoC integration. We exploit the Real-Time UML (RT-UML), SoC bus governed FPGA platform, and a waveform viewer reading test benches described in standard Hardware Description Language (HDL) such as Verilog. The RT-UML achieves fast design of master/slave wrappers, the FPGA platform reaches fast SoC integration with physical hardware prototype, and the waveform viewer accomplishes real world signal analysis. We begin at SDRAM controller and successfully transplant it to the FPGA platform. Firstly according to SDRAM specifications, we modify timing parameters according to the AC electrical characteristics. Secondly, according to the waveform defined in the AMBA specification, we draw out the Message Sequence Chart (MSC), and in accordance with the MSC we generate parameterized Finite State Machines (FSMs) for wrappers. Regarding the parameterized wrapper FSMs as templates, we wrap the SDRAM controller into an AMBA-compatible slave SIP. The AMBA SoC bus Analyzer, without interposing the bus transactions among SIPs under test, captures bus signals to external SDRAM. With programmable triggering conditions in complex logic, SoC engineers dump the signals before and after triggered point and analyze protocol compatibility using the waveform viewer. In this way, DMAs and user-defined ASICs are easily wrapped into platform-based and truly reusable SIPs. With the wrapper templates and the analyzer, we develop two types of direct memory access (DMA) prototypes including an independent DMA master/slave SIP and a dedicated DMA control framework that is integratible into memory-intensive SIPs. The wrapper templates, DMA prototypes, and the SoC bus analyzer constitute a reconfigurable SoC design framework. The statistical analysis suggests that the SoC design flow includes the proposed framework and gradually integrates verified SIPs. Therefore, providing real-world hardware rapid prototyping, the proposed framework effectively reduces complexity and uncertainty while increases reliability of SoC integration before the backend design stage.

Our IMS-T425 compatible Transputer design in FPGA has so far taken over 300 design days. Up to last year, minimal effort was spent for verification. Now a regression test bench has been brought in place, which is targeted to verify the design conformance after any changes. This T42 Transputer Verification Suite is based on a TVS-1 work from Michael Bruestle, and compares the register output of 54 selected instructions versus a true T425 golden reference for up to thousands of data samples. It has already helped in T42 micro-code debugging and hardware refinement.