Digital filtering and analysis for a semiconductor X-ray detector data acquisition

10 - Hardware and software development tools

This paper introduces a technique, called resynchronization, for reducing synchronization overhead in multiprocessor implementations of digital signal processing (DSP) systems. The technique applies to arbitrary collections of dedicated, programmable or configurable processors, such as combinations of programmable DSP's, ASICs, and FPGA subsystems. Thus, it is particularly well-suited to the evolving trend toward heterogeneous single-chip multiprocessors in DSP systems. Resynchronization exploits the well-known observation that in a given multiprocessor implementation, certain synchronization operations may be redundant in the sense that their associated sequencing requirements are ensured by other synchronizations in the system. The goal of resynchronization is to introduce new synchronizations in such a way that the number of original synchronizations that become redundant exceeds the number of new synchronizations that are added, and thus, the net synchronization cost is reduced. Our study is based on the context of self-timed execution for iterative dataflow specifications of DSP applications. An iterative dataflow specification consists of a dataflow representation of the body of a loop that is to be iterated indefinitely; dataflow programming in this form has been employed extensively in the DSP domain.

This paper describes the methodology that utilises some of the ATM traffic analysis techniques in the performance analysis of multichannel digital signal processing (DSP) systems. The analysed multichannel DSP systems employ statistical multiplexing in order to improve the DSP resource utilisation. A case study is used to illustrate the application of the proposed methodology. Performance of the studied system was estimated and it was shown that a significant efficiency gain may be achieved over the DSP systems that do not utilise statistical multiplexing of their resources.

Hereafter, we present an approach aiming to improve the reliability of digital signal processing (DSP) systems operating in real noisy (electromagnetic interference—EMI) environments. The approach is based on the coupling of two techniques: the “DSP-oriented signal integrity improvement” technique deals with increasing the signal-to-noise ratio (SNR) and is essentially a modification of the classic Recovery Blocks Scheme. The second technique, named “SW-based fault handling” aims to detect in real-time data- and control-flow faults throughout modifications of the processor code. When compared to conventional approaches using Fast Fourier Transform (FFT) and Hamming Code, the primary benefit of such an approach is to improve system reliability by means of a considerably low complexity, reasonably low performance degradation and, when implemented in hardware, with reduced area overhead. Aiming to illustrate the proposed approach, we implemented a HW/SW prototype to operate as a speech recognition system (SRS). This prototype was tested under a home-tailored EMI environment according to the IEC 61000-4-29 International Standard Normative. The obtained results indicate that the proposed approach can effectively improve the reliability of DSP systems operating in real noise (EMI) environments.

This paper presents a high-level synthesis methodology which may be applied to the synthesis of bit-serial, digit-serial or bit-parallel digital signal processing (DSP) systems. The methodology accepts as input a DSP system behavioral specification. The methodology provides for the optimization of DSP systems subject to constraints on throughput, IC area, data path width, and resource sharing strategies. The optimization technique is based on a generalized hill climbing algorithm known as simulated annealing. The output is control logic and data path specifications in a device independent hardware description language. Design examples of bit-serial and digit-serial filter realizations synthesized using the methodology are included.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The intense requirements of high-speed implementations of MultiDimensional (MD) Digital Signal Processing (DSP) systems justify the Application Specific Integrated Circuits (ASIC) designs and/or multiprocessor implementations. MD retiming has been recently proposed to improve the circuitry performance in high-level synthesis of single-rate MD DSP systems. This paper has conducted new theoretical analysis of MD multirate DSP systems modeled in data-flow graphs, and proposes intercalation of MD multirate systems so that unified MD retiming operations can be applied on multidimensional multirate DSP systems. By retiming and intercalation, full intra-iteration parallelism is achieved and functional elements can be executed simultaneously on circuits for the generic class of MD multirate DSP systems.KeywordsMultirate Signal ProcessingMD Data Flow GraphMultidimenional Retiming

The authors introduce a parallel DSP (digital signal processing) system called NOVI, consisting of 36 processor nodes. NOVI has a multicomputer architecture, which provides high programmability and effective scheduling capability. Its program-development-assist system facilitates powerful debugging functions to observe all states of NOVI and to control its execution. Each processor node comprises a transputer, a floating-point ALU (arithmetic logic unit), and 1 Mbyte of local memory, which can deal with even rather large tasks within a single node. An interconnection board allows easy reconfiguration into various network topologies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

International audience

With the improvement of Digital Signal Processor (DSP)&#x2019;s ability to process data, the requirement for memory access is higher and higher. In order to ensure the real-time performance of data processing, multiple processing stages including scalar execution level, access memory level in DSP core and peripherals like debug, the Host Port Interface (HPI) in DSP system needs to fetch or store data from memory more quickly. To solve this practical problem, this paper introduces a multi-port memory interface (MPMI) based on Advanced eXtensible Interface 4 (AXI4) bus protocol, which can connect multiple access ports in DSP system with Double Data Rate 4 (DDR4) Synchronous Dynamic Random Access Memory (SDRAM). The design has successfully passed the verification of various reading and writing scenarios, and the novel combination of fixed and polling priority makes the interface&#x2019;s access efficiency increase by 32&#x0025; compared with the one using a normal polling priority.

The requirement for efficient digital signal processing (DSP) systems and its solutions increases highly over the last few years. DSP techniques as well as its algorithms are necessary for day to day life tool namely smartphone, set-top unit (STU), video and acoustic players, digital cameras, digital television, etc. This paper describes a comparative study on knowledge-based digital filter structure namely transposed form, direct form, and systolic array. To implement the parallel processing the systolic array structure is often used. A Goertzel algorithm is implemented in the field-programmable gate array (FPGA) Altera EP4CE115F29C7 device which is used to determine the discrete Fourier transform (DFT). Finally, filtering technique is implemented efficiently by dividing filter coefficients and data into odd and even which increases the computational speed. The computational speed and functional verification results are achieved by using MATLAB. The Altera DSP builder and Simulink are used for the implementation of Goertzel algorithm. The 64-tap systolic low-pass filter structures offer 213.97-μs-less delay than the transposed form, 1700 μs, and direct form, 3900 μs, structures. Similarly for 2048-tap low-pass filter using sub-filter offers 49.397-ms computational speed and direct filtering offers 53.257 ms.

Editorial

A new highly integrated data acquisition (DAQ) system for a combined, APD-based, dual-modality PET/CT scanner, implementing both analog and digital electronics on the same board, has been fabricated and tested. The DAQ system was designed to achieve high-precision (<1 ns) coincidence detection in PET and high-rate event counting in CT imaging using the same detectors and electronics. One DAQ board holds 64 parallel detector channels that can be sampled directly at the output of the charge-sensitive preamplifiers (CSP) at a rate of 100 MHz with free-running analog-to-digital converters (ADC) from Maxim. Digital signal processing is performed in field programmable gate arrays (FPGAs) from Xilinx. Independent 500 V voltage regulators are mounted on board for optimum biasing of individual APDs coupled to phoswich detectors. The DAQ board has been fabricated on a 12 copper layers printed circuit board (PCB). The low-noise analog front-end is directly interfaced on board through differential CSP outputs to the high-speed digital circuits for optimum coupling and noise immunity. The board shows excellent electrical characteristics with all circuitry powered up, featuring a mean signal to noise and distortion ratio (SINAD) of 47.7 dB over all 64 channels when supplied with a 10 MHz sine waveform at its input. Initial performance characteristics with BGO/LSO phoswich detectors are reported.

Novel, efficient design methodologies are presented for the implementation of dedicated, multiprocessor digital signal processing (DSP) systems for high-speed, real-time applications. Specifically, a design process model consisting of three design phases is described. The first design phase is algorithm transformation, in which the DSP computing algorithms are reformulated and made suitable for parallel implementation. The second design phase is algorithm mapping and array configuration. During this phase, the parallel DSP algorithm is mapped to a systolic array. A multistage mapping procedure is presented. In the third design phase, the individual processing unit is designed. An optimal code-generation method for programming a multiple-DSP array is discussed. >

The current trends of advancement of memory technology indicates reasonable scope to have efficient memory-based computing systems as promising alternative to the conventional logic-only computing in order to meet the stringent constraints and growing requirements of the digital signal processing (DSP) systems in widely varying application environments. Several algorithms and architectures have been suggested in the literature to reduce the area- and time-complexities of commonly encountered computation-intensive cores of DSP functions by memory-based computing, but many more novel algorithms and architectures need to be developed to design flexible area-delay-power-efficient systems for various DSP applications.

1 - The basics