DYNAMIC EVOLUTION AND RECONFIGURATION OF SOFTWARE ARCHITECTURES THROUGH ASPECTS

Currently, most software systems have a dynamic nature and need to evolve at run-time. For this reason, the dynamic reconfiguration of software architectures is a challenge that must be dealt with to enable the creation and destruction of component instances and their links at run-time. This challenge is even greater when there are autonomous composite components which also need reconfiguration capabilities to evolve their internal compositions. This paper presents a novel approach to dynamically reconfigure software architectures taking advantage of aspect-oriented techniques. The approach presented is a platform-independent alternative whose aim is to increase the reuse and to decrease the maintenance effort. It deals with the challenge of reconfiguring composite components that: (1) are easy to maintain, since the dynamic reconfiguration concern is separated from the other concerns; (2) can autonomously reconfigure themselves, since each composite component is provided with dynamic reconfiguration services to change its internal architecture.

Application specific integrated circuits are used to provide real-time performance of handheld devices within the compact physical size and low energy dissipation. However, these circuits are inflexible for any modification like redesign and refabrication. Reconfigurable architectures are promising alternative for conventional computing devices such as application-specific integrated circuits. It provides high-level flexibility to adapt the applications through dynamic hardware customization even after fabrication. A reconfigurable computing system design considers the peculiarities of the targeted application domain along with architectural issues like dynamic reconfiguration, partial reconfiguration, hardware/software co-design and context management. A brief survey has been carried out to understand the concepts and applications of CGRA, FPGA, SoC, NoC, MPSoC, dynamic partial reconfiguration, hardware/software co-design, design-space exploration, multi-objective optimization, genetic algorithm and reconfigurable computing on wireless communications. This paper deals with the survey on modeling, design, implementation and evaluation of coarse-grained dynamically reconfigurable processor architectures targeting the real-time embedded computing domain.

Increasing penetration of DG brings many uncertain factors to the operation of the distribution network, which will increase difficulties for the recovery of power supply after the distribution network fault happens. Considering the real-time load demand and the random output changes of DG, this paper proposes a dynamic network reconfiguration method for distribution network fault recovery under high penetration of DG. First, a dynamic network reconfiguration model for distribution network fault recovery is established. Then, by introducing intermediate variables, a reasonable second-order cone relaxation is performed on the dynamic reconfiguration model. Third, the principle of dynamic islanding partition is introduced to coordinate with dynamic network reconfiguration. Finally, case studies are carried out on the IEEE 33-bus distribution network to illustrate the effectiveness of the proposed method.

In order to solve the problem of the complexity of software system and the efficiency of large-scale collaboration, software architecture design methods have gradually developed. In the process of software architecture evolution, users and concurrency are increasing day by day, and software technology is constantly evolving and improving accordingly. Although there are many researches and technical discussions on software architecture methodology, there are few papers that fully discuss the development of technology in terms of the evolution of the architecture. This paper takes the evolution of software architecture as the research object, discusses problems, solutions and related technologies involved in the evolution of software architecture, and comprehensively explains how the system gradually evolves from a single architecture to a complex high-concurrency architecture. KeywordsArchitecture designArchitecture evolutionHigh concurrency

Reconfiguration technique has been considered as one of the most promising electronic design automation (EDA) technologies in MPSoC design paradigms. However, due to the unavoidable latency in the reconfiguration procedure, it still poses a significant challenge to efficiently analyze the trade-offs for the software/hardware execution, static reconfiguration and dynamic reconfiguration. In this paper we first present a heterogeneous MPSoC middleware to support state-of-the-art dynamic partial reconfigurable technologies. Furthermore, we evaluate the reconfiguration latency and analyze the trade-off for the dynamic partial reconfiguration technologies.

With increasing demands and changing environment on software systems, a major challenge for those systems is to evolve themselves to adapt to these variations, especially during their running, where dynamic evolution of software architectures has been a key issue of software dynamic evolution research. Most current research in this direction focuses on describing dynamic evolution process of software architectures, and lack consistency analysis of dynamic evolution of software architectures. In this paper, we propose to represent software architectures with constraint hypergraphs, model dynamic evolution of software architectures with constraint hypergraph grammars, and discuss the consistency condition and corresponding consistency decision method of dynamic evolution of software architectures. Our approach provides a formal theoretical basis and a user-friendly graphical representation for consistency analysis of dynamic evolution of software architectures.

Welcome you to the Fifth Edition of the track Software Architecture: Theory, Technology, and Applications (SA-TTA 2017) as part of the 32th ACM/SIGAPP Symposium on Applied Computing (SAC).

In this paper, we propose a novel FPGA-based architecture for large-scale regular expression matching, called dynamic reconfigurable bit-parallel NFA architecture (Dynamic BP-NFA) that allows dynamic reconfiguration of the patterns using bit-parallel NFA-simulation. This is the first dynamic reconfigurable FPGA-based hardware with guaranteed performance for the class of extended patterns, where an extended pattern is a restricted regular expression in linear form consisting of letters, classes of letters, don't cares, optional letters, bounded and unbounded length gaps and repeatable letters. The key to our architecture is the use of bit-parallel pattern matching approach that has been developed in string matching communities for the decades. In this approach, the information of an input NFA is compactly encoded in bit-masks stored in a collection of registers and block RAMs. Then, the NFA is efficiently simulated by a fixed circuitry using a combination of bit- and arithmetic-operations on these bit-masks consuming one input letter per clock. As compared with the previous approaches of DFA-based dynamic reconfigurable architectures, experimental results show that the proposed architecture achieves higher throughput for the class of exact string patterns and comparable for the class of extended patterns.

Modern computing and network environments demand ahigh degree of adaptability from applications. At run time, an application may have to face many changes: in configuration, in protocols used, in terms of the available resources, etc. Many such changes can only be adequately addressed through dynamic evolution of the software architecture of the application. In this paper, we propose a novel approach to dynamically evolve a software architecture based on run-time aspect oriented programming. In our framework, a system designer/administrator can control the architecture of an application by dynamically inserting and removing code extensions. It is even possible to replace a significant part of the underlying middleware infrastructure without stopping the application. The novelty of this work is that it allows for a much more flexible development strategy as it delegates issues like middleware choice and adherence to an architectural specification to a framework enhanced by dynamic code extensions.

Dynamic software architectures are those that describe how components and connectors can be created, interconnected, and/or removed during system execution. Most existing architecture description languages (ADLs) provide a limited support to expressively describe these architectures and entail architectural mismatches and inconsistencies between architecture and implementation due to their decoupling from implementation. In this paper, we introduce the dynamic reconfiguration support provided by π-ADL, a formal, well-founded theoretically language for describing dynamic software architectures under structural and behavioral viewpoints. π-ADL provides architectural-level primitives for specifying programmed dynamic reconfigurations, i.e., Foreseen changes described at design time and triggered at runtime. In addition, π-ADL allows enacting dynamic reconfiguration by means of: (i) an exogenous approach, in which it is possible to control all elements of the software architectures and to apply the changes on the whole structure, and (ii) an endogenous approach, in which the architectural elements can manage dynamic reconfiguration actions. Furthermore, π-ADL is integrated with the Go programming language, thus enabling to automatically generate implementation code from architectural descriptions, thus tackling the existing gap between them. We hereby use a real-world flood monitoring system as an illustrative example of how to describe dynamic software architectures in π-ADL and automatically generate source code in Go.

Reconfigurable architectures become popular in consumer applications as they require low Non-Recurring Engineering costs. Certain FPGA families provide the Dynamic Partial Reconfiguration (DPR) mechanism which allows to modify parts of a device on-the-fly. The high reliability constraints in automotive systems requires safe communications between ECUs (Electronic Control Unit). This paper presents a support for fault-tolerant communication modes among ECUs by the use of the dynamic reconfiguration paradigm. Also in this paper, a method of integrating dynamic reconfiguration in Autosar environment is presented.

Software applications are continuing to grow at a rapid pace and became more and more complex. Thus, the use of software architectures in the development process is the ideal solution to deal with this issue. In this context, many Architecture Description Languages (ADLs) have been introduced to define the software architecture and its elements. Most of these ADLs do not address the dynamic behavior of the software architecture. This dynamic behavior is most commonly known as architectural reconfiguration. In our work, we use the Architecture Analysis and Design Language (AADL) due to its capacity to represent the architectural reconfiguration. However, AADL suffers from the absence of a concrete model to define its formal semantics. This paper presents a formal approach based on Bigraphical Reactive Systems (BRS) to model the dynamic architectural reconfiguration of embedded real-time systems expressed in AADL.

Large area/delay/power overheads are required to support the reconfigurability of field-programmable gate arrays (FPGAs). We proposed a hybrid CMOS/nanotechnology dynamically reconfigurable architecture, called NATURE, earlier to address this challenge. It uses the concept of temporal logic folding and fine-grain (i.e., cycle-level) dynamic reconfiguration to increase logic density and save area. Because logic folding reduces area significantly, most of the on-chip communications become localized. To take full advantage of localized communications, we then presented a new CMOS-based fine-grain dynamically reconfigurable (FDR) architecture. It consists of an array of homogeneous logic elements (LEs), which can be configured into logic or interconnect or a combination of both. FDR eliminates most of the long-distance and global wires, which occupy a large amount of area in conventional FPGAs. FDR improves the area-delay product by an order of magnitude relative to conventional architectures. In this paper, we present an augmented FDR 2.0 architecture, where: 1) the LE is augmented with dedicated carry logic to facilitate arithmetic operations; 2) diagonal direct links are incorporated to improve the flexibility of local communication; and 3) coarse-grain blocks, including embedded memories and digital signal processing (DSP) blocks, are added to support fast data-intensive computations. Experimental results show that the coarse-grain design can improve circuit performance by $3.6\times $ compared with the fine-grain FDR architecture. Incorporation of the DSP blocks in FDR 2.0 also enables more effective area-delay and power-delay tradeoffs, allowing the users to trade performance for smaller area or power consumption. We have implemented the design in the 22-nm FinFET technology, which enables more flexible and effective power management. Finally, different types of FinFETs and power management techniques have been explored in FDR 2.0 to optimize power.

Service-based applications are typically based on dynamic reconfiguration, since it can be regarded as compositions of multiple Web services. Because service-based applications usually run in open, dynamic, ever-changing environments, providing function-consistent application becomes a big challenge. The paper proposes an effective dynamic reconfiguration approach for services based applications. The approach tries to replace each faulty service firstly. If the attempts fail, it will construct regions for each faulty service and tries to replace the region. In order to ensure the correctness of dynamic reconfiguration, we use services-behavioral type to formally describe services and propose subtype rule services-behavioral type to judge the substitutability between services. Also, the case study is given to show that how to verify the correctness of dynamic reconfiguration.

Service-oriented architecture provides the ability to combine several web services in order to fulfil a user-specific requirement. In dynamic environments, the appearance of several unforeseen events can destabilize the composite web service (CWS) and affect its quality. To deal with these issues, the composite web service must be dynamically reconfigured. Dynamic reconfiguration may be enhanced by avoiding the invocation of degraded web services by predicting QoS for the candidate web service. In this paper, we propose a dynamic reconfiguration method based on HMM (Hidden Markov Model) states to predict the imminent degradation in QoS and prevent the invocation of partner web services with degraded QoS values. PSO (Particle Swarm Optimization) and SFLA (Shuffled Frog Leaping Algorithm) are used to improve the prediction efficiency of HMM. Through extensive experiments on a real-world dataset, WS-Dream, the results demonstrate that the proposed approach can achieve better prediction accuracy. Moreover, we carried out a case study where we revealed that the proposed approach outperforms several state-of-the-art methods in terms of execution time.