Handling the Dynamic Reconfiguration of Software Architectures Using Aspects

Change is an intrinsic property of software.A software system, during its lifetime, may require several updates, improvements, or new features.If these change requirements are not addressed, the risk of becoming a useless system increases.In fact, this is a challenging issue of safety-and mission-critical software systems, which cannot be stopped to perform maintenance or evolution operations due to their continuous operation.To reduce the aging of these critical systems, they must be provided with mechanisms enabling their dynamic evolution, i.e. the support of changes on their structure and behaviour while they remain in operation.This thesis is concerned with the design of a framework to build architecturebased, dynamically evolvable, software systems.The fact that this framework is a software architecture based approach provides the following advantages: (i) it offers a high-level of abstraction for describing dynamic changes; (ii) it allows varying the level of system description; and (iii) it advantages from the existing support for system modelling, code-generation, and formal analysis provided by architecture description languages.The framework presented in this thesis, called Dynamic PRISMA, is characterized by the combination of two levels of dynamism: Dynamic Reconfiguration, which addresses changes at the configuration level (i.e. the architectural configuration), and Dynamic Type Evolution, which addresses changes at the type-level (i.e. the specification of architectural types and instances).This combination is one of the major contributions of this thesis: thus a system is not only able to reconfigure at runtime the building blocks it is composed of (i.e.architectural types), but also to redefine these building blocks (or introduce new ones) at runtime.Another contribution of the thesis is the identification of the concerns related to dynamic evolution and their integration in the framework through aspects.This improves the separation of concerns and allows us to change reconfiguration specifications, evolution mechanisms, or the business logic independently of each other.A third contribution of this thesis is how this dynamism is supported: reconfiguration through autonomic capabilities, which provides proactivity according to either internal or external stimuli; and type evolution through asynchronous reflection, which enables the modification of a type specification and the transformation of their instances at different rates (i.e. when they are ready for evolution).Specifically, the asynchronous evolution vi semantics is precisely described by means of graph transformations.This formalism has been chosen because it naturally models both the system architecture and its asynchronous evolution.The work presented in this thesis is illustrated through a case study from the robotics domain; an area which could potentially benefit from the results of this thesis.

Application specific integrated circuits are used to provide real-time performance of handheld devices within the compact physical size and low energy dissipation. However, these circuits are inflexible for any modification like redesign and refabrication. Reconfigurable architectures are promising alternative for conventional computing devices such as application-specific integrated circuits. It provides high-level flexibility to adapt the applications through dynamic hardware customization even after fabrication. A reconfigurable computing system design considers the peculiarities of the targeted application domain along with architectural issues like dynamic reconfiguration, partial reconfiguration, hardware/software co-design and context management. A brief survey has been carried out to understand the concepts and applications of CGRA, FPGA, SoC, NoC, MPSoC, dynamic partial reconfiguration, hardware/software co-design, design-space exploration, multi-objective optimization, genetic algorithm and reconfigurable computing on wireless communications. This paper deals with the survey on modeling, design, implementation and evaluation of coarse-grained dynamically reconfigurable processor architectures targeting the real-time embedded computing domain.

Architectural mismatch; the semantic and syntactic gap preventing component composition, can be partially alleviated through the ubiquity of the protocols for service composition (syntax). And yet, the semantics of service or component composition have remained elusive. The contribution of this paper builds on the notions introduced by grammar-oriented object design (GOOD) using the notion of manners to specify the semantics of services and drive their automated composition through dynamically reconfigure architectures enabled through GOOD. This leads to the use of manners for explicit service semantics representation in a re-configurable architectural style. We describe the base requirements for automated component and services composition and show how automated assembly of components and services can be accomplished through a dynamically reconfigurable (DyRec) architectural style. In addition, we show how this vision of dynamic reconfiguration is naturally supported by the Web services framework, because it derives from some of the core requirements of the service oriented architectures (SOA) style embodied by Web services. Further, we discuss how such a DyRec architectural style can be implemented using grammar-oriented object design (GOOD) and describe a project that led to a tool called the Business Compiler, to accomplish dynamic composition and collaboration.

In this paper, we propose a novel FPGA-based architecture for large-scale regular expression matching, called dynamic reconfigurable bit-parallel NFA architecture (Dynamic BP-NFA) that allows dynamic reconfiguration of the patterns using bit-parallel NFA-simulation. This is the first dynamic reconfigurable FPGA-based hardware with guaranteed performance for the class of extended patterns, where an extended pattern is a restricted regular expression in linear form consisting of letters, classes of letters, don't cares, optional letters, bounded and unbounded length gaps and repeatable letters. The key to our architecture is the use of bit-parallel pattern matching approach that has been developed in string matching communities for the decades. In this approach, the information of an input NFA is compactly encoded in bit-masks stored in a collection of registers and block RAMs. Then, the NFA is efficiently simulated by a fixed circuitry using a combination of bit- and arithmetic-operations on these bit-masks consuming one input letter per clock. As compared with the previous approaches of DFA-based dynamic reconfigurable architectures, experimental results show that the proposed architecture achieves higher throughput for the class of exact string patterns and comparable for the class of extended patterns.

Large and complex decentralized systems with autonomous components often require appropriate mechanisms for cooperation, reliability, and dynamic reconfiguration. It is crucial that these mechanisms allow the system to execute continuously for a long period of time with minimal disruption, despite failure or reconfiguration of some components. They should also allow various components to interact in complex ways. We develop a uniform software architecture for implementing these mechanisms using generalized techniques and common functionalities. These mechanisms also support a variety of application-dependent policies. We present a manufacturing example that motivates our work.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

&lt;div class="section abstract"&gt;&lt;div class="htmlview paragraph"&gt;As powertrain hybridization technologies are becoming popular, their application for heavy-duty military vehicles is drawing attention. An intelligent design and operation of the energy management system (EMS) is important to ensure that hybrid military vehicles can operate efficiently, simultaneously maximize fuel economy and minimize monetary cost, while successfully completing mission tasks. Furthermore, an integrated EMS framework is vital to ensure a functional vehicle power system (VPS) to survive through critical missions in a highly stochastic environment, when needed. This calls for situational awareness and dynamic system reconfiguration capabilities on-board of the military vehicle. This paper presents a new energy management and control (EMC) framework based on holistic situational awareness (SA) and dynamic reconfiguration of the VPS. Typical results on a notional hybrid ground vehicle power system are presented to illustrate: 1) mission tasks power requirements and respective priority assignments; and 2) roles of situational awareness and dynamic reconfiguration layer in the operation of the proposed integrated energy management and control framework.&lt;/div&gt;&lt;/div&gt;

Dynamic software architectures are those that describe how components and connectors can be created, interconnected, and/or removed during system execution. Most existing architecture description languages (ADLs) provide a limited support to expressively describe these architectures and entail architectural mismatches and inconsistencies between architecture and implementation due to their decoupling from implementation. In this paper, we introduce the dynamic reconfiguration support provided by π-ADL, a formal, well-founded theoretically language for describing dynamic software architectures under structural and behavioral viewpoints. π-ADL provides architectural-level primitives for specifying programmed dynamic reconfigurations, i.e., Foreseen changes described at design time and triggered at runtime. In addition, π-ADL allows enacting dynamic reconfiguration by means of: (i) an exogenous approach, in which it is possible to control all elements of the software architectures and to apply the changes on the whole structure, and (ii) an endogenous approach, in which the architectural elements can manage dynamic reconfiguration actions. Furthermore, π-ADL is integrated with the Go programming language, thus enabling to automatically generate implementation code from architectural descriptions, thus tackling the existing gap between them. We hereby use a real-world flood monitoring system as an illustrative example of how to describe dynamic software architectures in π-ADL and automatically generate source code in Go.

Software applications are continuing to grow at a rapid pace and became more and more complex. Thus, the use of software architectures in the development process is the ideal solution to deal with this issue. In this context, many Architecture Description Languages (ADLs) have been introduced to define the software architecture and its elements. Most of these ADLs do not address the dynamic behavior of the software architecture. This dynamic behavior is most commonly known as architectural reconfiguration. In our work, we use the Architecture Analysis and Design Language (AADL) due to its capacity to represent the architectural reconfiguration. However, AADL suffers from the absence of a concrete model to define its formal semantics. This paper presents a formal approach based on Bigraphical Reactive Systems (BRS) to model the dynamic architectural reconfiguration of embedded real-time systems expressed in AADL.

Metric-based Evaluation of Implemented Software Architectures

Reconfigurable architectures become popular in consumer applications as they require low Non-Recurring Engineering costs. Certain FPGA families provide the Dynamic Partial Reconfiguration (DPR) mechanism which allows to modify parts of a device on-the-fly. The high reliability constraints in automotive systems requires safe communications between ECUs (Electronic Control Unit). This paper presents a support for fault-tolerant communication modes among ECUs by the use of the dynamic reconfiguration paradigm. Also in this paper, a method of integrating dynamic reconfiguration in Autosar environment is presented.

Large area/delay/power overheads are required to support the reconfigurability of field-programmable gate arrays (FPGAs). We proposed a hybrid CMOS/nanotechnology dynamically reconfigurable architecture, called NATURE, earlier to address this challenge. It uses the concept of temporal logic folding and fine-grain (i.e., cycle-level) dynamic reconfiguration to increase logic density and save area. Because logic folding reduces area significantly, most of the on-chip communications become localized. To take full advantage of localized communications, we then presented a new CMOS-based fine-grain dynamically reconfigurable (FDR) architecture. It consists of an array of homogeneous logic elements (LEs), which can be configured into logic or interconnect or a combination of both. FDR eliminates most of the long-distance and global wires, which occupy a large amount of area in conventional FPGAs. FDR improves the area-delay product by an order of magnitude relative to conventional architectures. In this paper, we present an augmented FDR 2.0 architecture, where: 1) the LE is augmented with dedicated carry logic to facilitate arithmetic operations; 2) diagonal direct links are incorporated to improve the flexibility of local communication; and 3) coarse-grain blocks, including embedded memories and digital signal processing (DSP) blocks, are added to support fast data-intensive computations. Experimental results show that the coarse-grain design can improve circuit performance by $3.6\times $ compared with the fine-grain FDR architecture. Incorporation of the DSP blocks in FDR 2.0 also enables more effective area-delay and power-delay tradeoffs, allowing the users to trade performance for smaller area or power consumption. We have implemented the design in the 22-nm FinFET technology, which enables more flexible and effective power management. Finally, different types of FinFETs and power management techniques have been explored in FDR 2.0 to optimize power.

Modern software systems, in particular distributed ones, are everywhere around us and are at the basis of our everyday activities. Hence, guaranteeing their correctness, consistency and safety is of paramount importance. Their complexity makes the verification of such properties a very challenging task. It is natural to expect that these systems are reliable and above all usable. i) In order to be reliable, compositional models of software systems need to account for consistent dynamic reconfiguration, i.e., changing at runtime the communication patterns of a program. ii) In order to be useful, compositional models of software systems need to account for interaction, which can be seen as communication patterns among components which collaborate together to achieve a common task. The aim of the Ph.D. was to develop powerful techniques based on formal methods for the verification of correctness, consistency and safety properties related to dynamic reconfiguration and communication in complex distributed systems. In particular, static analysis techniques based on types and type systems appeared to be an adequate methodology, considering their success in guaranteeing not only basic safety properties, but also more sophisticated ones like, deadlock or livelock freedom in a concurrent setting. The main contributions of this dissertation are twofold. i) On the components side: we design types and a type system for a concurrent object-oriented calculus to statically ensure consistency of dynamic reconfigurations related to modifications of communication patterns in a program during execution time. ii) On the communication side: we study advanced safety properties related to communication in complex distributed systems like deadlock-freedom, livelock-freedom and progress. Most importantly, we exploit an encoding of types and terms of a typical distributed language, session π-calculus, into the standard typed π-calculus, in order to understand the expressive power of concurrent calculi with structured communication primitives and how they stand with respect to the standard typed concurrent calculi, namely (variants) of typed π-calculus. Then, we show how to derive in the session π-calculus basic properties, like type safety or complex ones, like progress, by encoding.

We present an infrastructure for dynamic reconfiguration of heterogeneous coarse-grained reconfigurable architectures (CGRAs) based on our Gannet SoC platform. We introduce the infrastructure and in particular its domain-specific high-level programming language Gannet-C and discuss the language features that support dynamic reconfiguration and the way they are supported by the compiler and the hardware. We illustrate our approach with simulation results obtained using a cycle-approximate SystemC model of the Gannet platform.

Chapter 1 - Relating System Quality and Software Architecture: Foundations and Approaches

Field Programmable Gate Array (FPGA) has been widely adopted as modern reconfigurable computing platforms. Traditionally, the storage elements in FPGAs are static RAM (SRAM), which has large leakage power and limited scalability. Recently, non-volatile memory (NVM) is proposed to replace the SRAM in FPGA systems for static power and density considerations, at the cost of inducing larger dynamic power. Hybrid FPGAs combine the advantages of SRAM and NVM by employing both SRAM and NVM as logic storage elements. Although the feasibility of hybrid FPGA has been confirmed, the design flow has not fully explored the hybrid features yet, resulting in inferior system performance. Besides, traditional design flow does not consider the reconfiguration cost, which may prolong the reconfiguration procedures and thus degrade the system performance in dynamically reconfigurable FPGA systems. This work proposes a runtime and reconfiguration dual aware placement strategy for dynamically reconfigurable hybrid architecture. The proposed scheme considers the tradeoff between runtime and dynamic reconfiguration latency and optimizes the overall performance of the reconfigurable system. Evaluation shows that the proposed scheme improves the system performance by 14.6% for SRAM-MRAM hybrid FPGAs compared with the default placement strategy.