Dynamic reconfigurable bit-parallel architecture for large-scale regular expression matching

In the combination of the characters of the Matrix Multiplicative which are used in block cipher, a dynamic reconfigurable hardware architecture of Matrix Multiplicative is presented, which could be operated at a high speed and occupies a small area for the series of ciphers. The design has been realized using Altera’s FPGA of the family of Stratix II, and synthesized in 0.18 μm CMOS process. The result showed that the reconfigurable architecture has the advantage of flexibility and more effectiveness compared to the other designs at the area and the delay of the circuit.

Complex design, targeting System-on-Chip based on recon-figurable architectures, still lacks a generalized methodology allowing both the automatic derivation of a complete system solution able to fit into the final device, and mixed hardware-software solutions, exploiting partial reconfiguration capabilities. The Shining methodology organizes the input specification of a complex System-on-Chip design into three different components: hardware, reconfigurable hardware and software, each handled by dedicated sub-flows. A communication model guarantees reliable and seamless interfacing of the various components. The developed system, stand-alone or OS-based, is architecture-independent. The Shining flow reduces the time for system development, easing the design of complex hardware/software reconfigurable applications.

Application specific integrated circuits are used to provide real-time performance of handheld devices within the compact physical size and low energy dissipation. However, these circuits are inflexible for any modification like redesign and refabrication. Reconfigurable architectures are promising alternative for conventional computing devices such as application-specific integrated circuits. It provides high-level flexibility to adapt the applications through dynamic hardware customization even after fabrication. A reconfigurable computing system design considers the peculiarities of the targeted application domain along with architectural issues like dynamic reconfiguration, partial reconfiguration, hardware/software co-design and context management. A brief survey has been carried out to understand the concepts and applications of CGRA, FPGA, SoC, NoC, MPSoC, dynamic partial reconfiguration, hardware/software co-design, design-space exploration, multi-objective optimization, genetic algorithm and reconfigurable computing on wireless communications. This paper deals with the survey on modeling, design, implementation and evaluation of coarse-grained dynamically reconfigurable processor architectures targeting the real-time embedded computing domain.

K-nearest neighbour (KNN) is a supervised classification technique that is widely used in many fields of study to classify unknown queries based on some known information about the dataset. KNN is known to be robust and simple to implement when dealing with data of small size. However it performs slowly when data are large and have high dimensions. Therefore, KNN classifiers can benefit from the parallelism offered by Field Programmable Gate Arrays (FPGAs) to accelerate the algorithm. In addition, the KNN classifier is sensitive to the user defined parameter (K) which is the number of nearest neighbours. This parameter is known to affect the performance of the classifier; thus users would want the classifier to be easily adaptable to different values of K. In this work, we propose two adaptive FPGA architectures of the KNN classifier, and compare the implementations of each one of them with an equivalent implementation running on a general purpose processor (GPP). The proposed hardware implementations outperformed GPP by 76× for the first architecture and 68× for the second. In addition, we propose a novel dynamic partial reconfiguration (DPR) architecture of the KNN classifier, which allows for an efficient dynamic partial reconfiguration of a classifier implementation on FPGA for different K's. This DPR implementation offers 5× speed-up in the reconfiguration time of a KNN classifier on FPGA.

Constrained sequence alignment has been proposed as a way for incorporating biologists' knowledge about common structures or functions into the alignment process. For alignment of protein sequences, several studies have suggested taking into account the motifs (a restricted regular expression) from the PROSITE database to guide alignments. The regular expression constrained sequence alignment has been introduced for this purpose. An alignment satisfies the constraint if part of it matches a given regular expression in each dimension (i.e. in each sequence aligned). There is a method that rewards the alignments that include a region matching the given regular expression. This method does not always guarantee the satisfaction of the constraint. Another method constructs a weighted finite automaton from the given regular expression, and presents a dynamic programming solution that simulates copies of this automaton to find an alignment with maximum score satisfying the regular expression constraint. We propose a new algorithm for the regular expression constrained multiple sequence alignment problem. Our algorithm considers two layers each of which corresponds to part of the dynamic programming matrix for the alignment of the given sequences. We compute each layer differently using dynamic programming. We propose the following modification in the definition of the problem: the region satisfying the constraint does not contribute to the total score. This modification is not necessary for the correctness and the performance in certain cases such as the constraint involves only one motif or motif-matching regions span short distance in each sequence but we believe that with this modification we achieve the same goal by doing less work in practice. Our algorithm is much more efficient than a previously proposed algorithm that uses weighted automata, and its performance in practice is comparable to (and under certain conditions even better than) that of the ordinary (unconstrained) multiple sequence alignment algorithm. Our experiments on real biological sequences, and regular expressions each composed of a sequence of motifs verify this

This paper presents an emerging reconfigurable hardware that potentially delivers flexible high performance for cryptographic algorithms. MorphoSys, a dynamic reconfigurable architecture that sustains implementations that can yield into equally or even better performance results than custom-hardware and yet preserves all the flexibility of general-purpose processors. With today's great demand for secure communications systems, networks and the Internet, there is a growing demand for real-time implementation of cryptographic algorithms. As a case study, this paper presents the mapping and performance analysis for one of the five AES finalists cryptographic algorithms, namely RC6. Being an important and secure cryptographic algorithm, RC6 is considered well chosen to be mapped in order to test and evaluate the suitability of dynamic reconfigurable computer (RC) systems such as MorphoSys.

In recent years, dynamic reconfigurable processor which can achieve reconfiguration with a few cycles is proposed. The fast reconfiguration makes run-time reconfiguration possible, and the run-time reconfiguration gives a new possibility to the dynamic reconfigurable processor, i.e. the dynamic reconfigurable processor can also execute partitioned independent subtasks with repeated reconfigurations and executions. However, to achieve an execution with the run-time reconfiguration, performance should be evaluated with various overheads: reconfiguration, memory accesses, etc. The overheads depend on reconfigurable architectures, and it is generally difficult to evaluate the overhead. As the overhead may critically affect the performance, designers should carefully explore design space for suitable architectures. In this paper, we propose a dynamic reconfigurable architecture exploration method based on Parameterized Reconfigurable Processor model (PRP-model) and task partitioning optimization algorithm for architecture exploration corresponding to proposed PRP-model. Experimental results showed that the proposed PRP-model and the task partitioning algorithm for PRP-model can fast evaluate various reconfigurable architectures, and designers can easily find suitable reconfigurable architectures by changing the PRPmodel parameters.

Change is an intrinsic property of software.A software system, during its lifetime, may require several updates, improvements, or new features.If these change requirements are not addressed, the risk of becoming a useless system increases.In fact, this is a challenging issue of safety-and mission-critical software systems, which cannot be stopped to perform maintenance or evolution operations due to their continuous operation.To reduce the aging of these critical systems, they must be provided with mechanisms enabling their dynamic evolution, i.e. the support of changes on their structure and behaviour while they remain in operation.This thesis is concerned with the design of a framework to build architecturebased, dynamically evolvable, software systems.The fact that this framework is a software architecture based approach provides the following advantages: (i) it offers a high-level of abstraction for describing dynamic changes; (ii) it allows varying the level of system description; and (iii) it advantages from the existing support for system modelling, code-generation, and formal analysis provided by architecture description languages.The framework presented in this thesis, called Dynamic PRISMA, is characterized by the combination of two levels of dynamism: Dynamic Reconfiguration, which addresses changes at the configuration level (i.e. the architectural configuration), and Dynamic Type Evolution, which addresses changes at the type-level (i.e. the specification of architectural types and instances).This combination is one of the major contributions of this thesis: thus a system is not only able to reconfigure at runtime the building blocks it is composed of (i.e.architectural types), but also to redefine these building blocks (or introduce new ones) at runtime.Another contribution of the thesis is the identification of the concerns related to dynamic evolution and their integration in the framework through aspects.This improves the separation of concerns and allows us to change reconfiguration specifications, evolution mechanisms, or the business logic independently of each other.A third contribution of this thesis is how this dynamism is supported: reconfiguration through autonomic capabilities, which provides proactivity according to either internal or external stimuli; and type evolution through asynchronous reflection, which enables the modification of a type specification and the transformation of their instances at different rates (i.e. when they are ready for evolution).Specifically, the asynchronous evolution vi semantics is precisely described by means of graph transformations.This formalism has been chosen because it naturally models both the system architecture and its asynchronous evolution.The work presented in this thesis is illustrated through a case study from the robotics domain; an area which could potentially benefit from the results of this thesis.

Digital video decoding is a typical data-intensive video processing application. Currently, high throughput and real time processing are the fundamental demands of performance for video processing systems. With the development of various video standards, multi-standard applications have become another key feature. Thus, the high performance, low area cost and low power consumption make up the most important design targets when realizing video processing chips. Reconfigurable hardware architectures have been reviewed in this paper, which could meet the above requirements for multi-standard video decoders. Traditional reconfiguration methods usually decrease area cost by reconfiguring the interconnections among function units. A relatively new approach is dynamic reconfiguration, which could reconfigure hardware resources at runtime. Recently, a new method called Reconfigurable Video Coding (RVC) has come up, which is a library-based method to design a reconfigurable system for multi-standard video decoders. An overview of the methodologies for reconfigurable video processing system is shown in the paper, as well as case studies, which demonstrate the effectiveness of the design flow. The article presents some promising patents on design of reconfigurable architectures for multi-standards video decoder.

Dynamic software architectures are those that describe how components and connectors can be created, interconnected, and/or removed during system execution. Most existing architecture description languages (ADLs) provide a limited support to expressively describe these architectures and entail architectural mismatches and inconsistencies between architecture and implementation due to their decoupling from implementation. In this paper, we introduce the dynamic reconfiguration support provided by π-ADL, a formal, well-founded theoretically language for describing dynamic software architectures under structural and behavioral viewpoints. π-ADL provides architectural-level primitives for specifying programmed dynamic reconfigurations, i.e., Foreseen changes described at design time and triggered at runtime. In addition, π-ADL allows enacting dynamic reconfiguration by means of: (i) an exogenous approach, in which it is possible to control all elements of the software architectures and to apply the changes on the whole structure, and (ii) an endogenous approach, in which the architectural elements can manage dynamic reconfiguration actions. Furthermore, π-ADL is integrated with the Go programming language, thus enabling to automatically generate implementation code from architectural descriptions, thus tackling the existing gap between them. We hereby use a real-world flood monitoring system as an illustrative example of how to describe dynamic software architectures in π-ADL and automatically generate source code in Go.

The advantages and the flexibility introduced into the hardware implementation by partial dynamic reconfiguration have rapidly changed the design flow of embedded systems. Although nowadays it is common to deal with systems characterized by a dynamic architecture able to manage and to adapt themselves to extremely different working scenarios, it is not so easy to provide such flexibility also into the software part of these systems. In order to cope with this problem we developed an innovative modular Linux driver that greatly simplifies the software handling of reconfiguration, allowing the programmer to concentrate on a hierarchical view of the system to be implemented. This methodology can be applied to different architectures providing a powerful and flexible software solution and, at the same time, it can be easily customized to respond to specific behaviors and requirements

In this article we describe how to expand a partially dynamic reconfigurable pattern matcher for regular expressions presented in previous work by Divyasree and Rajashekar [2]. The resulting, extended, pattern matcher is fully dynamically reconfigurable. First, the design is adapted for use with parameterisable configurations, a method for Dynamic Circuit Specialization. Using parameterisable configurations allows us to achieve the same area gains as the hand crafted reconfigurable design, with the benefit that parameterisable configurations can be applied automatically. This results in a design that is more easily adaptable to specific applications and allows for an easier design exploration. Additionally, the parameterisable configuration implementation is also generated automatically, which greatly reduces the design overhead of using dynamic reconfiguration. Secondly, we propose a number of expansions to the original design to overcome several limitations in the original design that constrain the dynamic reconfigurability of the pattern matcher. We propose two different solutions to dynamically change the character that is matched in a certain block. The resulting pattern matcher, after these changes, is fully dynamically reconfigurable, all aspects of the implemented regular expression can be changed at run-time.

Since multimedia information is characterized by motley types of media with different properties, multimedia content retrieval in digital libraries requires dynamic reconfigurable architectures. In this paper, mobile agents are being used as the basis of such a dynamic reconfigurable architecture. The proposed architecture is further enhanced with innovative relevance feedback algorithms for interactive multimedia retrieval. In particular, an optimal recursive relevance feedback mechanism is examined by adoptively estimating a parametric correlation-based similarity measure. © 2005 IEEE.

Currently, most software systems have a dynamic nature and need to evolve at run-time. For this reason, the dynamic reconfiguration of software architectures is a challenge that must be dealt with to enable the creation and destruction of component instances and their links at run-time. This challenge is even greater when there are autonomous composite components which also need reconfiguration capabilities to evolve their internal compositions. This paper presents a novel approach to dynamically reconfigure software architectures taking advantage of aspect-oriented techniques. The approach presented is a platform-independent alternative whose aim is to increase the reuse and to decrease the maintenance effort. It deals with the challenge of reconfiguring composite components that: (1) are easy to maintain, since the dynamic reconfiguration concern is separated from the other concerns; (2) can autonomously reconfigure themselves, since each composite component is provided with dynamic reconfiguration services to change its internal architecture.

Self-adaptive systems evolve during system's execution against changes in operating environment. Such evolution and reconfiguration can be specified at architecture level using a syntactical expressive language such as Architecture Description Languages (ADLs). Variability modeling is an excellent instrument to model variations of software artifacts and their behavior within a self-adaptive system. However, existing ADLs that support dynamic reconfiguration do not explicitly model variation points on which the reconfiguration is based. This constitutes a barrier for a flexible management of reconfiguration at architecture level as well as traceability issues between a dynamic description given at architectural level and its counterpart at other abstraction levels. In this paper, we propose a variant-rich service-oriented ADL that enables system to reconfigure itself at runtime in response to a context change. To this end, our modular ADL, called Dynamic Service-Oriented Product Lines Architecture Description Language (DSOPL-ADL), specifies dynamic reconfigurations at architecture level besides specifying structural, variability and context information. Among several specified variable configurations at architecture level, one concrete configuration is generated at runtime triggered by a context value. Furthermore, an implementation code can be automatically generated from the architectural description.