The shining embedded system design methodology based on self dynamic reconfigurable architectures

In this paper, we propose a novel FPGA-based architecture for large-scale regular expression matching, called dynamic reconfigurable bit-parallel NFA architecture (Dynamic BP-NFA) that allows dynamic reconfiguration of the patterns using bit-parallel NFA-simulation. This is the first dynamic reconfigurable FPGA-based hardware with guaranteed performance for the class of extended patterns, where an extended pattern is a restricted regular expression in linear form consisting of letters, classes of letters, don't cares, optional letters, bounded and unbounded length gaps and repeatable letters. The key to our architecture is the use of bit-parallel pattern matching approach that has been developed in string matching communities for the decades. In this approach, the information of an input NFA is compactly encoded in bit-masks stored in a collection of registers and block RAMs. Then, the NFA is efficiently simulated by a fixed circuitry using a combination of bit- and arithmetic-operations on these bit-masks consuming one input letter per clock. As compared with the previous approaches of DFA-based dynamic reconfigurable architectures, experimental results show that the proposed architecture achieves higher throughput for the class of exact string patterns and comparable for the class of extended patterns.

In the combination of the characters of the Matrix Multiplicative which are used in block cipher, a dynamic reconfigurable hardware architecture of Matrix Multiplicative is presented, which could be operated at a high speed and occupies a small area for the series of ciphers. The design has been realized using Altera’s FPGA of the family of Stratix II, and synthesized in 0.18 μm CMOS process. The result showed that the reconfigurable architecture has the advantage of flexibility and more effectiveness compared to the other designs at the area and the delay of the circuit.

This paper presents an emerging reconfigurable hardware that potentially delivers flexible high performance for cryptographic algorithms. MorphoSys, a dynamic reconfigurable architecture that sustains implementations that can yield into equally or even better performance results than custom-hardware and yet preserves all the flexibility of general-purpose processors. With today's great demand for secure communications systems, networks and the Internet, there is a growing demand for real-time implementation of cryptographic algorithms. As a case study, this paper presents the mapping and performance analysis for one of the five AES finalists cryptographic algorithms, namely RC6. Being an important and secure cryptographic algorithm, RC6 is considered well chosen to be mapped in order to test and evaluate the suitability of dynamic reconfigurable computer (RC) systems such as MorphoSys.

In recent years, dynamic reconfigurable processor which can achieve reconfiguration with a few cycles is proposed. The fast reconfiguration makes run-time reconfiguration possible, and the run-time reconfiguration gives a new possibility to the dynamic reconfigurable processor, i.e. the dynamic reconfigurable processor can also execute partitioned independent subtasks with repeated reconfigurations and executions. However, to achieve an execution with the run-time reconfiguration, performance should be evaluated with various overheads: reconfiguration, memory accesses, etc. The overheads depend on reconfigurable architectures, and it is generally difficult to evaluate the overhead. As the overhead may critically affect the performance, designers should carefully explore design space for suitable architectures. In this paper, we propose a dynamic reconfigurable architecture exploration method based on Parameterized Reconfigurable Processor model (PRP-model) and task partitioning optimization algorithm for architecture exploration corresponding to proposed PRP-model. Experimental results showed that the proposed PRP-model and the task partitioning algorithm for PRP-model can fast evaluate various reconfigurable architectures, and designers can easily find suitable reconfigurable architectures by changing the PRPmodel parameters.

Since multimedia information is characterized by motley types of media with different properties, multimedia content retrieval in digital libraries requires dynamic reconfigurable architectures. In this paper, mobile agents are being used as the basis of such a dynamic reconfigurable architecture. The proposed architecture is further enhanced with innovative relevance feedback algorithms for interactive multimedia retrieval. In particular, an optimal recursive relevance feedback mechanism is examined by adoptively estimating a parametric correlation-based similarity measure. © 2005 IEEE.

We propose the use of a reconfigurable hardware architecture to reduce the power consumption of small sensor node that has various sensors and wireless communication facilities, that were the result of an adaptive function specialization mechanism. Traditional sensor nodes must have had a powerful and multi functional Micro-Controller Unit (MCU) to satisfy the requirements for processing any kinds of application. However, most of these systems only use a part of the functions provided by an MCU. In other words, such a unit often consumes a great dead of power for unused circuits. To avoid this situation, we propose the use of a reconfigurable architecture based on a Field Programmable Gate Array (FPGA) instead of an MCU because this array dynamically changes the circuit to the optimal one that is just used for the calculation required by an application. Moreover, we implemented a prototype system to do a preliminary evaluation of our proposed mechanism. In this evaluation, we show the performance of our proposed reconfigurable architecture by comparison with traditional architecture that uses processing time and power consumption. The experimental result shows that our proposed mechanism reduces enough power of its sensor nodes to prolong the lifetime of nodes without decreasing the processing time.

Online compression of I/O-data streams in Custom Computing Machines will enhance the effective network band-width of computing systems as well as storage bandwidth and capacity. In this paper a self-adaptive dynamic partial reconfigurable architecture for online compression is proposed. The proposed architecture will bring new possibilities in online compression due to its adaptivity to dynamic environments. In this study, network traffic, and input data distribution are considered as two dynamic behaviors. The degree of improvement provided by the architecture depends on data distribution, bandwidth, and available resources. Our analysis shows an improvement of up to 20% in compression ratios in comparison to non-adaptive approaches.

K-nearest neighbour (KNN) is a supervised classification technique that is widely used in many fields of study to classify unknown queries based on some known information about the dataset. KNN is known to be robust and simple to implement when dealing with data of small size. However it performs slowly when data are large and have high dimensions. Therefore, KNN classifiers can benefit from the parallelism offered by Field Programmable Gate Arrays (FPGAs) to accelerate the algorithm. In addition, the KNN classifier is sensitive to the user defined parameter (K) which is the number of nearest neighbours. This parameter is known to affect the performance of the classifier; thus users would want the classifier to be easily adaptable to different values of K. In this work, we propose two adaptive FPGA architectures of the KNN classifier, and compare the implementations of each one of them with an equivalent implementation running on a general purpose processor (GPP). The proposed hardware implementations outperformed GPP by 76× for the first architecture and 68× for the second. In addition, we propose a novel dynamic partial reconfiguration (DPR) architecture of the KNN classifier, which allows for an efficient dynamic partial reconfiguration of a classifier implementation on FPGA for different K's. This DPR implementation offers 5× speed-up in the reconfiguration time of a KNN classifier on FPGA.

Digital video decoding is a typical data-intensive video processing application. Currently, high throughput and real time processing are the fundamental demands of performance for video processing systems. With the development of various video standards, multi-standard applications have become another key feature. Thus, the high performance, low area cost and low power consumption make up the most important design targets when realizing video processing chips. Reconfigurable hardware architectures have been reviewed in this paper, which could meet the above requirements for multi-standard video decoders. Traditional reconfiguration methods usually decrease area cost by reconfiguring the interconnections among function units. A relatively new approach is dynamic reconfiguration, which could reconfigure hardware resources at runtime. Recently, a new method called Reconfigurable Video Coding (RVC) has come up, which is a library-based method to design a reconfigurable system for multi-standard video decoders. An overview of the methodologies for reconfigurable video processing system is shown in the paper, as well as case studies, which demonstrate the effectiveness of the design flow. The article presents some promising patents on design of reconfigurable architectures for multi-standards video decoder.

In finite impulse response (FIR) filters reconfigurability and low complexity are the two key requirements. In this paper FIR filter in transpose form with inherent pipelining are used to save computation time. A flow graph for transpose form block FIR filter with reduced complexity is derived on detail analysis of computation of transpose form block FIR filter. A generalised architecture which is multiplier based is derived for proposed transpose form block FIR filter for reconfigurable applications. A less complex design using multiple constant multiplications (MCM) method for block implementation of fixed FIR filter is also introduced.

High-performance analog and mixed-signal integrated circuits are integral parts of today's and future networking and communication systems. The main challenge facing the semiconductor industry is the ability to economically produce these analog ICs. This translates, in part, into the need to efficiently evaluate the performance of such ICs during manufacturing (production testing) and to come up with dynamic architectures that enable the performance of these ICs to be maximized during manufacturing and later when they're operating in the field. On the performance evaluation side, this dissertation deals with the concept of Built-In-Self-Test (BIST) to allow the efficient and economical evaluation of certain classes of high-performance analog circuits. On the dynamic architecture side, this dissertation deals with pipeline ADCs and the use of BIST to dynamically, during production testing or in the field, re-configure them to produce better performing ICs. In the BIST system proposed, the analog test signal is generated on-chip by sigma-delta modulation techniques. The performance of the ADC is measured on-chip by a digital narrow-band filter. When this system is used on the wafer level, significant testing time and thus testing cost can be saved. A re-configurable pipeline ADC architecture to improve the dynamic performance is proposed. Based on dynamic performance measurements, the best performance configuration is chosen from a collection of possible pipeline configurations. This basic algorithm can be applied to many pipeline analog systems. The proposed grouping algorithm cuts down the number of evaluation permutation from thousands to 18 for a 9-bit ADC thus allowing the method to be used in real applications. To validate the developments of this dissertation, a 40MS/s 9-bit re-configurable pipeline ADC was designed and implemented in TSMC's 0.25pm single-poly CMOS digital process. This includes a fully differential folded-cascode gain-boosting operational amplifier with high gain and high unity-

This paper delves into the fundamentals of hardware-software partitioning between an intelligent, generalized signal processor and reconfigurable hardware. A novel architecture is proposed for a RADAR control system and a design specification is illustrated with simulation results.

Within ubiquitous computing environments, services and devices can be dynamically adapted to changing conditions, and thus adaptivity becomes a key requirement in providing possibly better system performance. Most existing ubiquitous computing systems either support only software adaptation or manage reconfigurable hardware functions as conventional hardware devices. As a result, system adaptation and performance improvement are still restricted. To provide more robust system adaptation, we propose a self-adaptive hardware/software system architecture (SAHA) that consists of service suppliers, a hardware adapter, a system manager, an observer, and a reconfigurable hardware architecture. Further, SAHA supports both hardware preemption and hardware virtualization within a complete self-aware system adaptation mechanism such that the utilization of system resources is enhanced and better performance is provided for ubiquitous computing applications. Experiments with a ubiquitous computing service for information encryption demonstrate that SAHA can reduce the turnaround time by at least 11.9% of that required by using the conventional method.

In this paper we present two different, software and reconfigurable hardware, open architecture approaches to the PUMA 560 robot controller implementation, fully document them and provide the full design specification, software code and hardware description. Such solutions are necessary in today’s robotics and industry: deprecated old control units render robotic installations useless and allow no upgrades, advancements, or innovation in an inherently innovative ecosystem. For the sake of simplicity, just the first robot axis is considered. The first approach described is a PC solution with data acquisition I/O board (Humusoft MF634). This board is supported with Matlab Real-Time Windows Toolbox for real-time applications and thus whole controller was designed in Matlab environment. The second approach is a robot controller developed on field programmable gate arrays (FPGA) board. The complexity of FPGA design can be overcome by using a third party software package, such as self-developed Matlab FPGA Real Time Toolbox. In both cases, parameters of motion controller are calculated by using simulation of the PUMA 560 robot first axis motion. Simulations were conducted in Matlab/Simulink using Robotics Toolbox.

Reticle cost and cycle time to deliver new circuit design s to a wafer fab remain key focus areas for advanced semiconductor manufacturing and new product development. Resolution enhancement techniques like optical proximity correction as applied to critical layers ha ve increased the burden on mask data pr eparation and reticle writing steps of the mask making flow. The growing data volume and complexity of designs must be reduced to a perfect image on a reticle in the shortest time possible against computer and machine constraints. Continued dependence on 193 nm wavelength exposure in extremely low k 1 lithography exacerbates the underlying trends. Two important factors come together to drive the economics and performance of the reticle line: the complexity of the designs and the productivity of e-beam writing tools. The designs, OPC methods , and writing tool capabilities continue to evolve with each node of technology. The study builds on prior evaluations to look at fundamental pattern complexity across 90nm, 65nm, and 45nm logic designs using the gate and metal-1 critical layers. The writing tool throughput testing uses a range of standard patterns to establish shot limited performance as a calibration method for arbitrary designs. Node to node design and tool to tool generation comparisons highlight actual step changes in complexity and capability by introducing new quantitative methods, be nchmarking metrics, and testing strategi es. The findings are projected into the future using design complexity and writing tool trends to suggest implications about reticle cost, cycle time, or possible gaps in technology development. Keywords : mask data volume, pattern file size, RET, OPC, write time, data density, geometric content