Efficient FFT Implementation on a CGRA

This paper presents a high-level implementation of pipeline FFT. The design has been coded in Handel-C language and targeted Xilinx Virtex-E FPGA series. It is fully implemented and tested on real hardware using Celoxica RC1000-PP prototyping board. The implementation results show that our implementation outperforms other implementation of FFT on the same series of FPGA. An implementation of 1024-point FFT on Virtex-E can run at a maximum clock frequency of 82 MHz leading to a 82 MS/s throughput compared with the Xilinx core of the same size that can run at a maximum clock frequency of 83 MHz but with only 21 MS/s throughput. The design is parameterizable in terms of input wordlength, Twiddle factors wordlength and processing wordlength. It is scalable in terms of number of stages which means that a 16-point, 64-point, 256-point and 1024-point or higher power-of-4 complex-point FFT can be synthesized from the same code. The paper reports the fastest 1024-point FFT implementation on Virtex-E FPGA platform.

FFT is the fundamental unit of any signal processing system. Performance characteristics like speed, computational complexity and power consumption are dependent on FFT calculation. Optimizing FFT algorithm plays a significant role in optimizing the signal processing system. Hardware implementation of FFT follows a strict mathematical sense and hence has many problems with its VLSI realization. This paper presents the implementation of FFT algorithm based on pipeline architecture using the polyphase decomposition concept. The proposed architecture is designed to reduce the computational complexity and at the same time not compromising the speed of the overall DSP system. Polyphase decomposition is used to segment the long input sequence into P sub sequences by using decimation factor ‘P’. The FFT of these segmented sequences is computed serially by using pipelined Radix-2 MDC architecture with higher throughput rate. Finally, results are combined to get complete FFT of original sequence by using (P-1) adders and multipliers. In addition to this, the proposed architecture also allows the calculation of any “even-length” point FFT within a specified range which depends on the decimating factor. The computational complexity is reduced by a large factor when compared with the existing FFT algorithms. The use of MDC architecture ensures higher throughput compared to other existing architectures. The proposed architecture is more efficient than existing in terms of throughput rate and maximum clock frequency.

With an increasing number of processing elements (PEs) integrated on a single chip, fault-tolerant techniques are critical to ensure the reliability of such complex systems. In current reconfigurable architectures, redundant PEs are utilized for fault tolerance. In the presence of faulty PEs, the physical topologies of various chips may be different, so the concept of virtual topology from network embedding problem has been used to alleviate the burden for the operating systems. With limited hardware resources, how to reconfigure a system into the most effective virtual topology such that the maximum repair rate can be reached presents a significant challenge. In this article, a new approach using a maximum flow (MF) algorithm is proposed for an efficient topology reconfiguration in reconfigurable architectures. In this approach, topology reconfiguration is converted into a network flow problem by constructing a directed graph; the solution is then found by using the MF algorithm. This approach optimizes the use of spare PEs with minimal impacts on area, throughput, and delay, and thus it significantly improves the repair rate of faulty PEs. In addition, it achieves a polynomial reconfiguration time. Experimental results show that compared to previous methods, the MF approach increases the probability to repair faulty PEs by up to 50% using the same redundant resources. Compared to a fault-free system, the throughput only decreases by less than 2.5% and latency increases by less than 4%. To consider various types of PEs in a practical application, a cost factor is introduced into the MF algorithm. An enhanced approach using a minimum-cost MF algorithm is further shown to be efficient in the fault-tolerant reconfiguration of heterogeneous reconfigurable architectures.

Coarse-grained reconfigurable architectures aim to achieve goals of both high performance and flexibility. However, existing reconfigurable array architectures require many resources without considering the specific application domain. Functional resources that take long latency and/or large area can be pipelined and/or shared among the processing elements. Therefore, the hardware cost and the delay can be effectively reduced without any performance degradation for some application domains. We suggest such a reconfigurable array architecture template and a design space exploration flow for domain-specific optimization. Experimental results show that our approach is much more efficient, in both performance and area, compared to existing reconfigurable architectures.

A fault tolerant massively parallel processing architecture

This paper presents a method to time share the Processing Elements (PEs) of Runtime Coarse Grain Reconfigurable Architectures (CGRA) among multiple processes being executed concurrently onto the same CGRA. Runtime CGRA architectures time-multiplex the data path, creating a set of contexts for each state. These contexts configure the PEs and the routing resources of the CGRA and are typically loaded every clock cycle. The target architecture in this work is a commercial CGRA IP which is embedded as an IP into complex SoCs. Our proposed method analyzes the PE utilization in each context for multi-process systems running concurrently onto the same CGRA and time shares unused PEs assigned to one process with the other processes running in parallel. Our method reduces the total PE usage and hence the size of the CGRA IP and therefore the cost of the SoC. Results show that our method is extremely efficient and can reduce the PE utilization by up to 20% and on average by 14% and is only 2% worse than the optimal solution, while being much faster.

The MULTIPLUS project aims at the development of a modular parallel architecture suitable for the study of several aspects of parallelism in both true shared memory and virtual shared memory environments. The MULTIPLUS architecture is able to support up to 1024 Processing Elements based on SPARC microprocessors. The MULPLIX Unix-like operating system offers a suitable parallel programming environment for the MULTIPLUS architecture by providing facilities for the creation of threads, the allocation of private and shared memory space and the efficient use of synchronization primitives. After presenting the main features of the MULTIPLUS architecture and of the MULPLIX operating system, the paper describes in detail the design and the implementation of the three MULTIPLUS architecture basic hardware modules: the Processing Element, the Multistage Interconnection Network and the I/O Processor. In addition, the definition of the MULPLIX parallel programming primitives is discussed and their use is illustrated through an example. Finally, future directions in the development of the MULTIPLUS research project are commented.

This paper describes a new reconfigurable processor architecture specialized for high frame rate visual processing. This architecture employs a 2-D mesh processing element (PE) array in which the PEs can be configured to operate as SIMD arrays or operation-pipeline trees depending on image processing algorithms so that maximum on-chip memory consumption is reduced. To achieve high on-chip memory utilization, the architecture features that the instruction register in each PE is mapped in its local memory space and that the ALU network and the local memory network can be configured independently. Simulation results show that the proposed architecture effectively utilizes both of the SIMD and operation pipeline modes.

The architecture of an all gallium arsenide (GaAs) vector signal processor based on parallel GaAs 32-bit microproccessors is described. The vector processor includes a vector memory of 1 megabytes, a parallel operand bus architecture with eight parallel processing elements, and a control/scalar processor. The processing elements consist of a reduced instruction set computer with four floating-point coprocessors and local memory. This architecture has been evaluated using several benchmark programs, includinig complex FFT, complex inner product, and sort-and-merge routine. The results of this study indicate that the vector processor can perform a 1024-point complex radix-4 FFT, using 32-bit floating-point arithmetic, in 112 microseconds (350) megaflops) while consuming approximately 550 watts of power in a volume of approximately 0.1 cubic foot.

This paper describes the implementation of a FFT on a system based on a GP core and a reconfigurable coarse-grain accelerator. The entire system has been prototyped on an Altera Stratix II device. On the prototype a 1024-point FFT gives a 40X speed-up in comparison with the software implementation. The 1024-point FFT is executed in 400μβ. Considering an ASIC synthesis of the coarse-grain array, the 1024-point FFT is executed in 42μβ, against the 104μβ of a DSP implementation.

The Fast Fourier transform (FFT) is a bandwidth-limited algorithm. To alleviate the bandwidth requirement, shared memory is commonly used to accommodate intermediate data. However, given the limited capacity of shared memory in state-of-art GPUs, the intensive shared-memory usage of FFT reduces the number of thread blocks/workgroups that can run concurrently on a streaming multiprocessor/compute unit. In this work, we present our solution, called shared-memory multiplexing, to make more effective use of shared memory. Shared-memory multiplexing is built on a key observation that allocated shared memory is not utilized throughput the lifetime of a thread block/workgroup. We propose our pure software approaches to enable multiple thread blocks to time-multiplex shared memory so as to increase the number of concurrent thread blocks/workgroups on each streaming multiprocessor/compute unit. The improved thread-level parallelism introduces significant performance gains for FFT. On an NVIDIA GTX 480 GPU, our FFT kernel outperforms the NVIDIA library CUFFT V4.0 by 21 % for a 1 k-point FFT with a batch size of 2,048. On an NVIDIA Tesla K20c GPU, our FFT kernel outperforms the NVIDIA library CUFFT V5.0 by 58 % for the same inputs.

This paper evaluates the tradeoffs involved in the design of the software-extended memory system of Alewife, a multiprocessor architecture that implements coherent shared memory through a combination of hardware and software mechanisms. For each block of memory, Alewife implements between zero and five coherence directory pointers in hardware and allows software to handle requests when the pointers are exhausted. The software includes a flexible coherence interface that facilitates protocol software implementation. This interface is indispensable for conducting experiments and has proven important for implementing enhancements to the basic system.Simulations of a number of applications running on a complete system (with up to 256 processors) demonstrate that the hybrid architecture with five pointers achieves between 71% and 100% of full-map directory performance at a constant cost per processing element. Our experience in designing the software protocol interfaces and experiments with a variety of system configurations lead to a detailed understanding of the interaction of the hardware and software components of the system. The results show that a small amount of shared memory hardware provides adequate performance: One-pointer systems reach between 42% and 100% of full-map performance on our parallel benchmarks. A software-only directory architecture with no hardware pointers has lower performance but minimal cost.

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs such as H.264/AVC and MPEG4. With the proposed specific instructions and hardware accelerators, it can handle the processing requirement of High Definition (HD) video. With parallel SAD Processing Elements (PEs) using pattern information, the proposed IME instruction supports not only the full search algorithm but also other fast search algorithms. The gate count is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP with sixteen PEGs runs at 160MHz and can handle 1080p@30 frame in realtime.

SIMD processors are increasingly used in embedded systems for multi-media applications because of their area- and energy-efficiency. Communication between the processing elements (PEs) in an SIMD processor has remained a cause of inefficiency however; the SIMD concept prescribes that all PEs communicate in the same clock cycle. Existing SIMD architectures solve this problem either by multi-hop communication (causing cycle overhead), or by a fully connected communication network (causing area overhead). To solve the communication bottleneck, we propose a reconfigurable SIMD architecture (RC-SIMD) with a set of delay-lines in the instruction bus, distributing the accesses to the communication network over time. We can (re-) configure the size and number of delay-lines, a specific configuration representing a trade-off between the number of clock cycles and the length of a clock period. Reconfiguration time is typically much less than 1% of the execution time of an algorithm, and the extra configuration hardware is less than 2%. Experiments show that our reconfigurable architecture achieves (on average) more than 10% performance improvement over a non-reconfigurable architecture.

Coarse-grained reconfigurable architectures (CGRA) require many processing elements and a configuration memory unit (configuration cache) for reconfiguration of the ALU array elements. This structure consumes significant amount of power. Power reduction during reconfiguration is necessary for the reconfigurable architecture to be used as a competitive IP core in embedded systems. In this paper, we propose a power-conscious reusable context pipelining architecture for CGRA that efficiently reduces power consumption in configuration cache without performance degradation. Experimental results show that the proposed approach saves up to 57.97% of the total power consumed in the configuration cache with reduced configuration cache size compared to the previous approach.