Electrical modeling of 3D stacked TSV

The technology of 3D IC integration is highly probable to achieve the demand for high performance, better reliability, miniaturization and lower-priced portable electronic products. Since the through silicon via (TSV) is the heart in 3D IC integration architectures, the reliability issues of TSV interconnects should be extremely concerned. Due to the large thermal expansion mismatch among the Cu, Si, and SiO 2 , the induced thermal stresses and strains can occur and become the driving forces for failures in TSV interconnects. Hence, the stress analyses and failure mode investigation for TSVs are in urgent need. Among the typical failures, the mostly common failure type is delamination, which will be caused when lower energy release rate (ERR) or higher critical stresses at interfaces are presented. In this study, the finite element modeling (FEM) for a symmetrical single in-line copper filled TSV with redistribution layer is illustrated. Two kinds of horizontal cracks that embedded in the interface of SiO 2 passivation and Cu seed layer (Cu pad delamination cases) are introduced to realize the interfacial ERR, where is also the critical stress area that observed from finite element analysis. The significance of design parameters such as crack length, TSV diameter, TSV pitch, depth of TSV, SiO 2 thickness and Cu seed layer thickness are also brought up. The methodology of design of experiments (DoE) has been adopted to capture the most important mechanical parameters of the TSV to comprehend the corresponding ERR. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3D IC integration.

Three-dimensional (3D) integration of silicon microelectronic devices improves the electronic functions of devices and minimizes packaging density drastically. A through-silicon via (TSV) structure is indispensable for maximizing the density of interconnections among the stacked silicon chips. However, since the TSV structure is surrounded by silicon, and there is large mismatch in materials properties between metallic materials used for the TSV structure and silicon, thermal stress is essentially generated around the TSV structure during their fabrication process and operating conditions. Recently, electroplated copper thin films have started to be applied to the interconnection material in the TSV structure because of its low electric resistivity and high thermal conductivity. However, the electrical resistivity of the electroplated copper thin films surrounded by SiO2 was found to vary drastically comparing with those of the conventional bulk material. This was because that the electroplated copper thin films consisted of grains with low crystallinity and grain boundaries, in other words, abnormally high defect density. Thus, both the crystallinity and electrical properties of the TSV structure was investigated quantitatively by changing their electroplating conditions and thermal history after the electroplating. It was observed that many voids and hillocks appeared in the TSV structures depending on the electroplating conditions. It was also found that the stress-induced migration occurred after the high temperature annealing which was introduced for improving the crystallinity of the electroplated films. Therefore, it is very important to evaluate the crystallographic quality of the electroplated copper thin films after electroplating to assure both the mechanical and electrical properties of the films.

Through silicon vias (TSVs) provide advanced vertical interconnections solutions for system-in-package (SiP) (such as chip to chip, chip to wafer, and wafer to wafer stacking), wafer-level packaging, interposer packaging. At present the shortest electrical path (vertical electrical feed through) between two sides of a silicon chip is one of the important applications. In order to achieve high density and high performance package, TSVs technology has been developed. And for three-dimensional (3D) MEMS (Microelectromechanical System) packaging, TSVs are the most important enabling technology. In this paper, some advantages of TSVs technology are described, and process flow of TSVs module is introduced firstly. Subsequently, a novel electricity test method of Non-Ideal Planes for TSVs is introduced. Finally, many critical issues and challenges of TSVs are reviewed.

Defect isolation and failure analysis is a key factor that drive development and manufacturing yield improvements in semiconductor packaging industry. From a manufacturing point of view, ensuring adequate package reliability is becoming more challenging due to increasing packaging complexity and a more pronounced impact from material physical property mismatch among packaging materials and components. The task of isolating defects and finding root cause is further complicated by ever shrinking feature sizes within the device and/or package, already approaching the nanometer range in contemporary semiconductor packages. Conventional failure analysis techniques such as physical cross sectioning or micro-cutting using focused ion beams(FIB) are sometimes no longer sufficient to find these defects. Both physical cross section and FIB are only capable of exposing the defect in two dimensions (x and y directions), which makes pinpointing the defect in depth, i.e., the z direction, extremely difficult when dealing defects with micron and submicron size. Additional complications are many times introduced during conventional sample preparation, which can introduce undesirable artifacts associated with the module and/or device depackaging. These artifacts may mask the true defects, or lead to misinterpretation of the true cause of failure. In this work, it has been determined that a three-dimensional failure analysis method is critical for finding some defects in silicon packages. For example, xenon difluoride (XeF2) has excellent selectivity to silicon and provides efficient material removal by chemical reaction, generating gaseous by-products that can be readily exhausted [1]. Furthermore, XeF2 has very little reaction with non-silicon materials, such as SiO2, and the metals and polymers commonly used in semiconductor devices and packages. This paper reports the application of XeF2 as an effective failure analysis technique to reveal defects in silicon packages. The mechanism of selective reaction between XeF2 and Si is discussed and key design features of the failure analysis tool are presented. The paper also highlights a few case studies which advantageously utilize XeF2 etching to expose defects. XeF2 was especially effective in detecting the source of electrical leakage in 3D packages having Through Silicon Via (TSV) structures. Due to its high etching selectivity to silicon, the leakage area in electrically failing samples was found to be due to damage of the TSV liner (passivation layer material) and further analysis reveals a three dimensional view of the TSV defect. With the addition of XeF2 etching, further characterization of defects by traditional methods such as FIB micro cutting also becomes more practical. The work suggests that a wider application of Si removal via XeF2 can be achieved by combining mechanical milling of bulk silicon followed by a final, low stress, silicon removal by XeF2 etching.

A novel Through Silicon Via (TSV) structure to mitigate the high electrical loss at high frequency is presented here. At low frequency, the loss for the TSV is caused mainly by the material loss of the Silicon (Si) substrate due to its low resistivity. However, at millimetre wave (mmWave) frequency range, especially above 50GHz, in addition to the insertion loss, the return loss due to impedance mismatched becomes significant. These losses become a serious setback for the Si Interposer for the mmWave applications. To overcome these losses, polymer cavity formed in the Si substrate with TSV is developed. The polymer has lower loss tangent and lower dielectric constant than Si. These properties can help to reduce the insertion loss and the return loss. Depending on the requirement, multiple set of TSV can be formed on the polymer cavity to provide higher interconnect density. From the simulation results, the new polymer cavity TSV at 100GHz have an insertion loss and return loss of ~0.2dB and less than -25dB, respectively. On the other hand, conventional high resistivity TSV has an insertion loss and return loss of ~1.4dB and more than -10dB, respectively, at the same frequency. For higher frequency range, the performance of the polymer cavity TSV is approximately consistent, but the conventional TSV deteriorated drastically. In this paper, the design, fabrication process and the measurement results are presented. The prototype polymer cavity TSV via-line-via test vehicle has a measured insertion loss of less than 1dB and a return loss of better than -10dB through the frequency range up to 110Gz.

Three-dimensional integration is considered as one of the effective methods that continue the rapid development of microelectronic technology for More than Moore. Through Silicon Via (TSV), which is used to connect signals on different layers, is the critical factor of three-dimensional integration technology. Because of its lower thermal resistance, TSV is also beneficial for heat dissipation. In order to verify the feasibility of using TSV as an internal nested heat dissipation structure in three-dimensional systems, an analytical model of internal heat transfer of a power chip with TSV was proposed. Based on the proposed theoretical model, the thermal resistance of the vertical silicon path and the TSV path is 32.4K/W and 5.34K/W, respectively. It is proved to be feasible that using TSV for internal heat dissipation of a power chip. The simulated results of the thermal resistance on the two paths are nearly consistent with the theoretical ones. So, the analytical model of the heat transfer is correct and validated.

In this study, an on chip bus driver TEG (test element group) has been developed for the data transmission performance at TSVs for 3D IC integration. The on chip bus driver TEG consists of transceiver (TX), receiver (RX) and TSV group which has 2, 4 and 8 TSVs for the analysis of the TSV transmission performance with different load effects which are caused by different number (2, 4, and 8) of chip stack (each chip is with one TSV). This chip has been made by TSMC's 0.18μm process (FEOL) and ITRI's BEOL process. The square chip area is 1.69mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and power supply voltage is 1.8V with 30μm diameter TSVs on 30μm pitch and 100μm depth. Finally, a design guide line and a test tool will be proposed with the present on chip bus TEG.

This paper taking the microstrip-via hole-microstrip interconnect structure of microwave multi-chip modules (MMCM) as the research object establishes the simulation model of the via hole structure and using Ansoft HFSS simulation software analyzes the effects of the structure parameters of the connecting angle θ between microstrip and via hole, the via hole aperture, the via hole length and the size of pad on the scattering parameters of the signals. The influence law of the structure parameters of the number of uniform coaxial shield via hole and the distance from the shield via hole to the interconnect via hole on the parameters of signal scattering properties is studied by establishing the model of coaxial line structure and a low pass filter circuit. The research shows that: the impedance mismatch generated by reflection could be reduced and signal transmission performance will be improved by appropriate expanding the circular pad at joints between interconnect via hole and microwave transmission line. In 0~16.5GHz frequency channel, the signal transmission has a good performance when θ close to 0° and get worse when θ equals to 30°. In 16.5 to 20GHz band, the signal transmission performance will become better and better with the angle θ increases, and the best transmission performance is obtained when θ close to 180° with the relatively low reflection. Therefore, joint angle θ should be controlled within 30° in the microstrip line wiring. The effect magnitude order of Interconnect via hole structure parameters on the signal transmission performance is, the via hole diameter D > the via hole length H > the pad diameter D. When other parameters remains constant, the via hole diameter is directly proportionate to S11 and inversely proportional to S21, that is to say the performance of signal transmission will become worse with the via hole diameter increasing. The larger the pad diameter, the greater is the parameter S11 and the reflected energy. The larger the size of the pad, the smaller is the parameter S21 and the signal transmission coefficient. The increasing of the via hole length will lead to deterioration of impedance discontinuities to cause more serious reflection, meanwhile, the insertion loss will increase, the return loss will decrease, the frequency of the first resonance point will decrease, the performance of the signal transmission will degrade. Therefore, comprehensive consideration of the curve that the insertion loss varies with TDR, the length of via hole should be controlled less than 1mm. The addition of the coaxial shield via hole around the interconnected via hole can improve the scattering properties of the signal. In the range of X-band of 8~12GHz, when the shield via hole radius is 0.1mm, the via hole number is 6, the equivalent coaxial outer conductor radius is 0.8mm, the via hole height is 0.8mm, the signal transmission loss with the shielded via hole is nearly less 0.45dB than without it and the signal transmission has a better performance.

3-D integration technologies offer significant advantages to develop multiprocessor systems-on-chip with embedded memory. Reliable power distribution is a challenging issue in these systems due to multiple planes and through silicon vias (TSVs). The two primary TSV technologies, via-first and vialast, have been evaluated for power delivery in a 32 nm 3D system with eight memory planes and one processor plane. Since the impedance characteristics of via-first and via-last based TSVs are significantly different due to distinct filling materials and dimensions, the power distribution network in each case exhibits different design requirements. A valid design space is identified for both cases. Despite the low parasitic resistance of a via-last TSV, a power network based on via-last TSVs produces signal routing blockages. Furthermore, via-last TSVs exhibit high inductive behavior, producing a non-monotonic design space. It is demonstrated that via-first TSVs can satisfy the power supply noise at the expense of 7.5% additional area as compared to via-last TSVs.

A double-sided and ultrathin 3-D glass interposer with through package vias (TPVs) at same pitch as through silicon vias (TSVs) in silicon interposers is developed to provide a compelling alternative to 3-D IC stacking of logic and memory devices with TSVs. The 3-D IC stacking approach to achieve high bandwidth has several drawbacks, including the need for TSVs through the logic die, thermal management within the 3-D stack, and the high manufacturing cost associated with wafer-based TSV processing. This paper presents design, fabrication, and electrical characterization of small TPVs (15–40 $\mu{\rm m}$ in diameter) in 30- $\mu{\rm m}$ thin glass to achieve an ultrathin 3-D interposer. This paper also reports the first demonstration of ultrasmall TPVs in glass (15 $\mu{\rm m}$ ) with same dimensions as TSVs in silicon. The signal insertion loss and crosstalk behavior of TPVs in ultrathin glass were investigated and found to be superior to TSVs using 3-D electromagnetic simulations. In demonstrating the 3-D interposers, two process-related challenges were addressed in this paper, namely: 1) defect-free formation of ultrasmall TPV holes with diameters of 15 $\mu{\rm m}$ at 27- $\mu{\rm m}$ pitch and 2) TPV metallization with copper. The fabricated TPVs in ultrathin glass showed a good model to hardware correlation of signal transmission with insertion loss ${ at 20 GHz. The results in this paper suggest that the 3-D interposer concept can be a simpler alternative to 3-D IC stacking with TSVs to achieve high bandwidth between the logic and memory devices.

Through Silicon Via (TSV) can be used to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1-3]</sup> . Via Reveal-a kind of wafer back side process moduleplays an important role in the successful implementation of TSV. In via-first and via-mid TSV integration flows, Si must be removed from the backside of the wafer to make contact with the bottom of the TSVs. This operation is performed using a mechanical grind followed by a reveal etching process. So in this paper, we will focus on the TSV reveal unit process. Firstly, we will briefly review TSV integration technology; Then a set of experiments is described which were used to select etch parameters to achieve the desired etching rate, selectivity and profile. Lastly we will show the results of TSV reveal using wet etching process. The proper composition of the HNO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /HF/CH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> COOH(HNA) solutions, etching parameter, and TEOS deposited by proper temperature provide the necessary process control and etching selectivity that enable the use of higher throughput wet etch for TSV back etch.

In this paper, the design, fabrication, and high-frequency characterization of three types of nontraditional through-silicon via (TSV) technologies are discussed. First, the integration of TSVs within a silicon microfluidic heat sink is presented; TSVs are fabricated within a pin-fin heat sink, and the frequency response of TSVs within a deionized-water-filled silicon pin-fin heat sink is experimentally analyzed. Second, to electrically shield the signal transmission of such TSVs, coaxially shielded TSVs consisting of multiple ground TSVs surrounding a single signal TSV are demonstrated. It is experimentally shown that as the number of ground TSVs increases, shielding is improved. Finally, a partial air-isolation technique is proposed to reduce TSV loss and capacitance at high frequencies.

Low cost wafer-level chip-scale vacuum packaging (WLCSVP) imposes unique constraints on potential implementation of through-silicon vias (TSVs). A WLCSVP requires a relatively thick substrate to prevent mechanical failure. Two approaches for integrating TSVs in thick silicon wafers have been successfully demonstrated. Both approaches enable TSV formation from the backside of a device wafer and are compatible with the requirements of subsequent packaging operations. We achieved low contact resistance between TSVs and frontside Ti/Cu and Al metallization, while demonstrating high isolation resistance and high TSV yield.

In this paper, we present test structures and measurement techniques that enable the extraction of the significance of the thermal–mechanical stress in 3D-stacked integrated circuit technology. Heaters and integrated diodes have been used to determine the impact of hotspots in 3-D systems. The results obtained showed that in 3-D case, the peak temperature of a hotspot is three times higher compared to a traditional 2-D system. For the characterization of through silicon vias (TSVs)-induced stress and its impact on analog metal-oxide semiconductor (MOS) devices, a 10-bit current steering digital-to-analog converter (DAC) test structure is utilized. The DAC has been optimized to detect ion changes down to 0.5% due to TSV proximity, TSV orientation, thermal hotspots, and wafer thinning or stacking process. The results obtained from stand-alone short-channel MOS devices and the DAC structure clearly indicate the impact of TSV proximity and TSV orientation on the carrier mobility of nearby transistors.

3D chip stacking with through silicon vias (TSVs) has been identified as one of the major technologies for achieving higher silicon packaging density and shorter interconnect. The test vehicle presented in this paper is a 3D chip stack package. Each layer of the test vehicle has two silicon flip chips mounted at the bottom of a silicon interposer with solder bumps. The flip chip has the equivalent dimensions and pad patterns as commercial memory chips. The interposer, with multiple interconnect TSVs for electrical connection and a central TSV for underfill dispensing, can function as a logic chip or as a redistribution chip in a real application. The assembly steps of the test vehicle include conductive adhesive filling for the interconnect TSVs, bonding two bumped flip chips on an interposer (to form a single layer), vertical stacking of the single layers and underfill dispensing. For the filling of the interconnect TSVs, an auger-dispensing method is first adopted to overfill the interconnect TSVs, followed by removing the excessive adhesive beyond the interconnect TSVs by squeegeeing. A jet valve continuously dispenses free dots of an underfill encapsulant into the central TSVs. The central TSVs function as an entrance for underfill dispensing and an uninterrupted point-source to provide fluid for each layer. The free dots form a capillary flow to fill the under-chip spaces of the test vehicle. The usage of TSVs rather than chip edges eliminates the presence of a wide edge reservoir, resulting in smaller ‘keep-out’ area occupation on the substrate.