Elementary Explanation: How “Boundary Scan Test” Works

Board-level boundary scan testing, focusing largely on the boundary scan EXTEST mode for structural testing of interconnects between boundary scan devices on a board and testing of conventional, nonscan components which cannot be accessed using traditional in-circuit or cluster test techniques, is dealt with. Strategies and test-nail placement for implementing various types of boundary scan testing are detailed. The strategies discussed are virtual interconnect, virtual in circuit, standard cluster testing, and virtual cluster testing. It is shown that, where restricted physical access hampers in-circuit or cluster testing, virtual access provided by boundary scan device leads may offer the means of assuring a comprehensive test. When both physical and virtual access is needed, this requirement must be taken into account during board design and factored into board layout to ensure successful implementation of the test.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper describes the use of boundary scan based tests and embedded built in test (BIT) software in the manufacturing defects testing of a 100 MHz, high density, surface mount multi-chip-module, parallel processing computer.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The components and the solder joints that are made during assembly to hold components to their printed circuit board can suffer from defects and therefore need to be tested. Many research papers on board-Assembly testing focus on boundary scan test, processor-controlled test, or other powered digital testing techniques that mostly ignore the indispensable passive circuits and that can incur damage that could have been avoided by executing a non-powered test first. In-circuit testing is a non-powered test method that applies stimuli and measures responses using probe needles. However, often used self-learning solutions for designing these tests need a known-good-board, entailing significant disadvantages. In this paper, a software tool is described that automatically generates in-circuit tests based on the product design files, without requiring probe access on every net. Furthermore, the tool indicates where on the board fault coverage is not maximal, and hence where extra probe access will improve the test quality.

This paper focuses on the practical aspects of combining boundary scan testing with traditional In-Circuit Test. The fault coverage, diagnostic, fixturing, and throughput benefits that can be realized by testing with a combined BSCAN/ICT strategy are described, along with the specific issues and challenges involved in providing a comprehensive BSCAN/ICT solution.

Two generations of High Definition Television decoders have been developed and produced. Boundary scan test was successfully implemented in the latter generation, and proved to be the design for test solution for the future.

From the viewpoint of a casual observer, it appears that less than 10% of the paper and panel presentations at ITC in the last 10 years have been related to board test. Of those, the majority have focused on boundary scan testing. Note that both IEEE 1149.1 and IEEE 1149.4 are standards for IC’s. Board testing continues to be a significant challenge for producers of both high volume and high complexity PWA’s. The impact of a poor board/system test strategy is felt even more by contract manufacturers. So why is it, then, the board and system test are not receiving more attention at ITC?

Detectability of Resistive Open Defects in Assembled PCB Circuits by Boundary Scan Testing after Shipping to a Market

We have been developing radiation-hardened optically reconfigurable gate array (ORGA) VLSIs. The ORGA- VLSIs allow the programmable gate array to be broken partly. In this case, radiation-damaged regions are avoided and non-damaged regions are only used for applications. However, to exploit the advantage point of ORGAs, the faulty regions must be identified prior to the use. Although JTAG interface is useful for identifying the faulty region, current JTAG interface is vulnerable to radiation. To solve this problem, we have developed a new radiation-hardened JTAG interface that is compliant with IEEE 1149.1, by applying triple modular redundancy to current JTAG interface. The designed JTAG interface was implemented onto an FPGA to test an optically reconfigurable gate array VLSI. The ORGA operation was verified using the open-source debugging tool OpenOCD and SVF files. At that time, boundary scan tests were successfully completed for the ORGA-VLSI. This paper presents the experimental results.

A novel test strategy, the Loop Testing Architecture (LTA), is introduced to reduce aliasing probability and testing time for multichip modules. This is accomplished by connecting cascadable built-in testers (CBITs) in neighboring pipelined stages to increase the length of the test suites. Fundamental properties of the LTA supporting randomness in the generated test patterns (state coverage) and the asymptotic aliasing probability are presented. Results on two small-scale multiprocessor configurations show that the aliasing probability in analyzing signatures is comparable to that of an MLFSR but with fairly low area overhead; compared with the circular self-test path technique, less testing time is required by LTA. Further evaluation of the potential capabilities provided by the LTA compared with boundary scan and other pipelined test scheduling approaches confirmed the usefulness of LTA as a framework for designing effective testable systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper presents an interactive MS-Windows(R)-based framework for high-level specification and analysis of tests on printed circuit boards, using the IEEE 1149.1 standard, and also on integrated circuits using scan design like the LSSD testing methodology. As novel contributions we provide an object-oriented tool for Boundary Scan and LSSD test automation with support for remote tests, including interfaces to circuit description, chip interconnection, test vector analysis and test vector generation. The system includes features like remote testing (using client-server technology), project management, menu-based command entry, user-defined configuration and a comprehensive set of commands.

Design for Testability (DFT) provides for economic benefits and reduction in costs for design, manufacturing and support of electronic systems. The amalgamation of increased benefits and net reduced costs is value enjoyed throughout the life cycle of the system. While a number of formulas have been developed over the years to justify DFT, a unifying methodology is needed that can be used to calculate the overall economic value of DFT. The methodology we use in this paper relates known input benefit and cost parameters and map their dependencies to higher level DFT benefits and costs. This method demonstrates the numerous ways DFT can improve a system's life cycle value. It can also be used to justify the costs of DFT, such as added engineering labor, additional parts, higher cost boundary scan and built-in self test (BIST) parts. Moreover, they help convince financially focused management that DFT is a worthwhile investment even though the expenditures are in the early part of the life cycle and the return on that investment may be years later. Proponents of DFT need the methodology we present here to back up their assertions that DFT is profitable. Using dependencies lends itself to programming and calculations of DFT value can be readily performed by spreadsheet programs.

This article discusses the development of a board level manufacturing test for a surface mount board implemented with boundary scan. The board examined is a composite of several actual products. Methods for effectively developing a boundary scan test are examined along with some of the advantages of approaching the development in unique ways. Additionally, the criteria for using these methods are developed. Results for test development time and the resulting test coverage show that with two weeks of test development using boundary scan it is possible to increase the rate of solder opens detection from 80% to 99% for a large ball-grid-array module.

This paper proposes a novel boundary scan test scheme for intellectual property (IP) core identification via watermarking. The core concept is embedding a watermark identification circuit (WIC) and a test circuit into the IP core at the behavior design level. The procedure depends on current IP-based design flow. This scheme can detect the identification of the IP provider without the need to examine the microphotograph after the chip has been manufactured and packaged. This scheme can successfully survive synthesis, placement, and routing and identify the IP core at various design levels. Experimental results have demonstrated that the proposed approach has the potential to solve the IP identification problem.

In this paper, we present a methodology for synthesizing testability features in a design described using Hardware Description Language (HDL) and the Synopsys Test Compiler tool. Because an HDL described design of an IC device can be automatically transformed into a gate-level implementation for a given technology with Synopsys Synthesis Tools, adding internal scan test circuitry or boundary scan test circuitry can be easily achieved with the Synopsys Test Compiler. We will discuss scan styles, test methodologies, test pattern generation, as well as the application and format of test patterns.

JTAGバウンダリスキャンテストの現状と展望