Evolutionary design of polymorphic gates using ambipolar transistors

A general design approach to design polymorphic circuits with polymorphic gates is proposed. These polymorphic circuits can adaptively adjust their functionalities with the changes of the electrical characteristics of components induced by the change of environment. The single function circuits that can work correctly and maintain their functionalities in different environments can be regarded as a special kind of polymorphic circuits. The general design approach for these circuits is proposed, and based on this approach, the general design approach to designing polymorphic circuits is also proposed. It is proved that a polymorphic circuit with any two different functions in two different environments can be implemented with a complete polymorphic gate set, and a definition on the gate set is given and the completeness is also discussed. Finally, these general design approaches are analysed and some experiments are performed to demonstrate their efficiency.

In this paper a state of the art, main problems and future trends concerning evolutionary design of combinational digital circuits are presented. Several evolutionary algorithms for design and optimization of combinational digital circuits are also shortly described. In evolutionary design methods the main problem is related to "combinatorial explosion" existing in those methods. Because evolutionary design methods are based on "generate and test" model, therefore together with growing of digital circuit input number, the number of potential combinations which must be tested are growing exponentially. This problem is a "bottle-neck" of those methods, and therefore it is discussed in details in this paper. To solve this problem it becomes important to elaborate efficient decomposition techniques of the designed circuits to some less complex sub-circuits, and then to design each of them independently. Also, it is important to create novel genetic operators (as mutation and crossover) which will always lead to acceptable solutions (solutions which satisfy the truth table). Due to such kind of operators, any repair mechanisms need not necessarily be used, and therefore the "generate and test" model will be simplified only to generation of new solutions, and therefore evolutionary design methods will become more effective.

TFETs arise as promising devices for low power and low voltage applications, since they don’t present a subthreshold slope limit of 60 mV/dec like in MOSFETs (1-3) and also show higher intrinsic voltage gain (AV) than the conventional MOS transistors (4). Furthermore, in order to improve the performance and the scaling, the nanowire structure for this technology has been studied (5). From simulations, it was observed that the predominant conduction mechanism and the interactions between the diagonally opposite surfaces of the nanowire TFETs are changed when the transistor diameter is reduced. When the transistor is biased in “strong inversion”, the predominant conduction mechanism near the silicon/oxide interface is the band-to-band tunneling (BTBT). However it is known that there is a gradual transition of mechanisms along the source/channel junction. As a consequence, coming closer to the center of the nanowire, the trap-assisted tunneling (TAT) influence becomes higher. In the center and nearby regions, where the energy bands of source and channel at the interface are far from being overlapped and therefore there is no tunneling occurrence, the conduction occurs through SRH mechanism. This work focuses on the impact of the nanowire diameter reduction on the main analog performance parameters. This analysis will be performed both experimentally and by simulations. The studied devices were fabricated at IMEC, Belgium. The gate stack consists of 3nm of HfO2 on 1nm, 10nm TiN and 30nm amorphous silicon. The measured devices contain 400 nanowires in parallel. The difference between the abrupt and the non-abrupt TFETs process resides in the source doping process. In the first and in the latter, a boron in-situ doping and a boron ion implantation were performed, respectively (5). The main difference between MOSFETs and TFETs is the conduction mechanism, since TFETs operate through tunneling mechanisms while MOSFETs are based on drift/diffusion (fig.1). Considering that the devices with a large diameter are biased in “strong inversion” condition, the TFETs present a higher intrinsic voltage gain (AV­) than the MOSFETs (fig.2). Although the transconductance (gm) of the MOSFETs is higher, TFETs are less affected by the electric field from the drain and thus have a good output characteristic (lower gd values). For devices with smaller diameters in the “strong inversion” condition, in which an interaction between the potential of the opposite surfaces appears and the symmetrical BTBT regions becomes closer to each other, Av is degraded due to the stronger dependence of BTBT on the drain voltage, causing a higher gD(fig.3). Due to this interaction, the BTBT predominance begins to occur at a lower gate voltage for nanowires with smaller diameter (fig.4). Since TFETs have been studied for low voltage applications, the analog analysis is also performed in “weak inversion”. When a TFET is biased in this condition, the efficiency (gm/ID) is higher for smaller diameter devices (fig.5). This happens owing to the higher percentage of the junction, in which the predominant occurring mechanism is BTBT, if compared with larger devices. Consequently, the value of gm is higher for smaller nanowires. AVwas calculated using equation [1] and the results are presented in table 1. Considering the “weak inversion condition”, there is a point of maximum AV for a specific diameter and a degradation for smaller and larger nanowire diameters because of a competition between both effects, the increase of gm/ID and the decrease of the Early voltage (VEA) with the reduction of the diameter. The VEA decrease is caused by the higher dependence of the current conduction on the drain voltage, since for the smaller devices, BTBT predominates along the entire source/channel junction. From a large to a narrow nanowire, the BTBT regions from opposite surfaces become even closer. The diameter for which these regions start to overlap, is the one associated with maximum AV. Therefore, it is possible to conclude that the decrease of the intrinsic voltage gain for larger diameters is more dependent on the transistor efficiency, and for narrower diameters it is more dependent on the Early voltage. Besides the larger diameter nanowire TFETs, which show better analog behavior than MOSFETs in “strong inversion” (this result was also found for FinFET structures (4)), the smaller diameter devices show potentialities for low power and low voltage applications, since their AV is better for low gate voltages than for the larger diameter NW-TFETs. (1) W.M.Reddick et al.,Appl.Phys.Lett.,67, 494-496,(1995). (2) T.Krishnamohan et al.,Techn,Dig.IEDM,947-950,(2008). (3) A.S.Verhulst et al.,J.Appl.Phys.,104(6),(2008). (4) P.G.Agopian et al.,TED,60,2493-2497,(2013). (5) A.Vandooren et al., Solid State Electronics, Vol.72, 82-87,(2012). Figure 1

This paper applies the Monte Carlo method to study junctionless transistors in order to define trade-offs in the configuration of the channel and compare the results with conventional MOS transistors.

The preparation and characteristics of the solid-state field-effect transistor (FET) based on poly(p,p'-biphenol)(PBP) thin film prepared by electropolymerization of p,p'-biphenol are presented. The PBP-based FET displayed excellent drain current (ID)-drain voltage (VD) characteristics for various gate voltages. The ID-VD characteristics were analyzed as in a conventional MOS transistor.

Main goal of this paper is to propose a compact library of polymorphic gates based on suitable type of reconfigurable transistors. In fact, their exploitation brings a significant advantage for space-efficient synthesis of complex polymorphic circuits. Actual behaviour of those transistors closely depends on so called ambipolar property. That particular aspect simply allows the selection of n- or p- channel operating mode of the transistor structures which is controlled by means of switching the voltage level at a dedicated control electrode. The gates were developed by an evolution approach using Cartesian genetic programming. Various discrete switch-level ambipolar transistor models extended by taking into account the threshold voltage drop degradation effect were used. A diverse range of polymorphic gates were designed, which clearly shows significant transistor savings compared to the conventional approaches. Finally, the individual components that belong to the library also suggest the opportunity how to considerably reduce the target size of complex polymorphic circuits.

This paper shows that the evolutionary design of digital circuits which is conducted at the gate level is able to produce human-competitive circuits at the transistor level. In addition to standard gates, we utilize unconventional gates (such as the NAND/NOR gate and NOR/NAND gate) that consist of a few transistors but exhibit non-trivial 3-input logic functions. Novel implementations of adders and majority circuits evolved using these gates contain fewer transistors than the smallest existing implementations of these circuits. Moreover, it was shown that the use of these gates significantly improves the success rate of the search process.

Reliability of Diode-Integrated SiC Power MOSFET(DioMOS)

Conventional metal oxide semiconductor field-effect transistor (MOSFET) devices exhibit short-channel issues and struggle to scale down their dimensions in the ultra-nanoscale regime. To continue the development in the electronics industry, it is needed to shift the conventional transistor technology to another direction, where the transistor-less idea can be implemented for the design of logic circuits. To achieve the goal of high-performance and scalable technology, a transistor-less technology, called quantum-dot cellular automata (QCA) nanotechnology, got much attention due to its numerous benefits in comparison to the conventional semiconductor devices. The QCA nanotechnology provides highly dense and fast-operating circuits with minimal energy dissipation. The exclusive OR (XOR) operation is a key logic in digital system design. Therefore, this paper proposes a single-layer; unique XOR gate in the QCA nanotechnology using the idea of cell translation in order to minimize the number of QCA cells and latency, and it is simulated using the QCA Designer-E tool. The proposed XOR gate is further applied for the implementation of half-adder and full-adder circuits and successfully verified their functions. The energy dissipation for all the circuits is estimated using the QCA Pro tool. The proposed designs are compared with the existing designs to outline the importance. The proposed XOR gate minimizes the design cost by 1.21X and energy dissipation by 16.87% at the 1.5 kink energy level as compared to the best-reported work in the literature.

Traditional circuit design does not scale well to large, complex problems. Nature solves the scalability problem by using a complex mapping implicit in the process of biological development. By modelling this process we aim to improve scalability in evolutionary circuit design. Here we extend our earlier work (Gordon and Bentley, 2002) by demonstrating that evolution can learn and encode useful circuit design abstractions in a developmental process. We go on to present enhanced models of development with improved intercellular communication and show how this improves their ability to generate circuits.

In recent years the evolution of digital circuits has been intensively studied. This paper proposes an elitist pool evolutionary algorithm based on novel approach in order to improve evolutionary design of logic circuits in efficiency and capability of optimization. In the process of evolution, a novel sub-circuit crossover strategy can improve the local optimization by inheriting the better parts of two parental circuits, and an adaptive mutation strategy based on importance of gene-position can maintain the diversity of a population. Experiments show that the proposed method is able to design logic circuits efficiently.

The Floating Gate MOS Transistor with Multiple Inputs is a device that offers some advantages with regard to the conventional MOS transistor. However, even today, there is a lack of formal and detailed analysis about the analog model in the literature. An accurate model of this device is very important for designing high performance analog cells. In this document a strategy for modeling the floating gate transistor operating in the weak inversion region based in the adaptation of the EKV model is proposed. The basis for developing a complete theory which allows the modeling of this device model is introduced. This type of modeling can be very useful for high performance analog integrated circuits designers where the transistor concerned here is strongly recommended. Further, this modeling process is also useful for the development of new computational tools for analog circuits simulation.

A combinational circuit design method that can be completely implemented on a FPGA is presented. For carrying out faster evolution in evolutionary circuit design, a sub population based MOEA (multiobjective evolutionary algorithm) is employed in which the reconfigurable circuit (RC) architecture is encoded by Cartesian Genetic Programming (CGP). For hardware implementation, the Celoxica RC1000 PCI is employed which includes Xilinx Virtex xcv 2000E FPGA chip. This PCI card is communicating with host PC and acting as an evolvable platform. MOEA adopted modules are designed into a FPGA chip for discussing the rationality of circuit design method. Results of direct evolution and results of incremental evolution is compared, it shows MOEA is most efficient in the aspect of speeding up the convergence of evolution.

Multifunctional Logic Circuits In article number 2109491, Yutaka Wakayama and co-workers demonstrate electrically reconfigurable organic logic circuits using a dual-gate anti-ambipolar transistor. The transistor shows a negative differential transconductance even at room temperature. This unique feature achieves five two-input logic gate operations with “only a transistor”. Such logic operations are not obtainable in conventional transistors. The device concept will provide a way of realizing multifunctional organic logic circuits using a simple circuit design.

Hybrid-phase-transition FETs (Hyper-FETs) are recently proposed steep switching devices that utilize the phase transition materials (PTM) to achieve a boost in the ratio of ON ( ${I}_{{{\mathrm {ON}}}})$ and OFF currents ( ${I}_{{{\mathrm {OFF}}}})$ . Prototypical demonstrations of the Hyper-FET have shown performance improvement in comparison with conventional transistors, which motivates the evaluation of its device-circuit design space. In part I, we analyze the device aspects establishing the effects of the resistivity and phase transition thresholds of the PTM on the characteristics of Hyper-FETs. Our analysis shows that the ratio of insulating and metallic state resistivity ( $\rho _{\mathrm {INS}}$ and $\rho _{\mathrm {MET},}$ respectively) of the PTM needs to be higher than the ${I}_{{{\mathrm {ON}}}} /I_{{{\mathrm {OFF}}}}$ of its host transistor to achieve performance improvement in Hyper-FET. For a host transistor with $I_{{{\mathrm {OFF}}}} = 0.051\mu \text{A}/\mu \text{m}$ and ${I}_{{{\mathrm {ON}}}} = 191.5\mu \text{A}/\mu \text{m}$ , $\rho _{\mathrm {MET}} .cm and $\sim 7.5~\Omega $ .cm $ .cm is required to achieve proper device functionality with a boost in ${I}_{{{\mathrm {ON}}}}/{I}_{{{\mathrm {OFF}}}}$ . Additionally, we establish the ranges of phase transition thresholds that yield proper functionality of the Hyper-FETs considering different ${I}_{{{\mathrm {OFF}}}}$ targets. The methodology of choosing appropriate PTM geometry to achieve the target device characteristics is also described. We show that with proper design, Hyper-FETs achieve 94% larger ${I}_{{{\mathrm {ON}}}}$ at iso- ${I}_{{{\mathrm {OFF}}}}$ compared with a FinFET. We examine the circuit design aspects of Hyper-FET in part II.