Exploring the rogue wave phenomenon in 3D power distribution networks

This paper addresses the modeling and analysis problems for power distribution networks (PDNs) in 3-D ICs. An on-chip distributed model is proposed for 3-D power grids, in which the details of metal layers are considered. The distributed model is demonstrated to be essential to identifying the unique noise behavior of 3-D PDNs. A lumped model is proposed based on the distributed model. The lumped model features the connection impedance between tiers and is proven to be useful for designers to understand the global effects of 3-D PDNs. Based on the models, an analysis flow is designed for 3-D PDNs in both frequency domain and time domain. With the analysis flow, the electrical characteristics of 3-D PDNs are studied systematically for the first time. The frequency-domain analysis identifies the global and local resonance phenomena in 3-D PDNs that are distinct from those in 2-D PDNs. The physical mechanisms behind the resonance phenomena are investigated. The time-domain analysis predicts the worst-case supply noise based on distributed current constraints. The “Rogue Wave” concept is introduced to explain the spatial and temporal relations of the worst-case on-chip noise responses in 3-D PDNs.

The impedance characteristics of a power distribution system are analyzed in the previous chapter based on a one-dimensional circuit model. While useful for understanding the principles of the overall operation of a power distribution system, a one-dimensional model is not useful in describing the distribution of power and ground across a circuit die. The size of an integrated circuit is usually considerably greater than the wavelength of the signals in the power distribution network. Furthermore, the power consumption of on-chip circuitry (and, consequently, the current drawn from the power distribution network) varies across the die area. The voltage across the on-chip power and ground distribution networks is therefore non-uniform. It is therefore necessary to consider the two-dimensional structure of the on-chip power distribution network to ensure that target performance characteristics of a power distribution system are satisfied. The on-chip power distribution network should also be considered in the context of a die-package system as the properties of the die-package interface significantly affect the constraints imposed on the electrical characteristics of the on-chip power distribution network.

Three-dimensional (3D) integration is envisioned as a natural defense to thwart side-channel analysis (SCA) attacks. However, there lack extensive studies on the unique feature of 3D power distribution network (PDN) noise and its impact on the efficiency of SCA attacks in 3D chips. This work fills the gap. Our experiments based on the real PDN and through-silicon via (TSV) models indicate that the noise from the other 3D planes is additive, which can significantly change the power profile of the crytpo unit in a 3D chip. We exploit the cross-plane PDN noise to develop a new counter-measure against the correlation power analysis (CPA) attacks in 3D integrated circuits (ICs). Simulation results show that the proposed method successfully improves the system resilience against CPA attacks and enhances the correlation difference by 29.1% and 18.7% over 2D and 3D baseline, respectively.

EVs are recognized as distributed loads and power sources with random motion characteristics in the power distribution networks (PDN); therefore, they serve as connecting points for the distribution network and transportation network (PDN-TN), and have significant impact on the stability and reliability of the routine operation of the coupled networks. In order to guarantee the safe operation of PDN-TN, it is necessary to evaluate the reliability of this coupled network. In this paper, the trip chaining theory is applied to describe the travel plan of EVs, and semi-dynamic flow allocation (SDTA) method is adopted to propose a simulation calculation method of energy flow between two networks based on user equalization (UE) criterion. The new reliability evaluation index for energy flow between the coupled networks is further proposed to better evaluate the reliability. Taking into account the daily trip characteristics of EVs, vehicles types, and charging modes, a coupled network reliability evaluation method based on sequential Monte Carlo simulation is put forward. Finally, the practicability of the proposed method is verified by an IEEE-RBTS BUS-6 test system and a 12-node transportation network.

This paper deals with the use of the integrated circuit electromagnetic model (ICEM) to analyze, predict, and optimize autocompatibility and electromagnetic emission at chip and system level. ICEM is currently under standardization process (IEC62014-3). The basic ICEM architecture is composed of a power distribution network model and an internal current source modeling digital activity. Such an approach enables the description of any kind of digital or mixed-signal design. This model is useful either for the IC manufacturer or the system manufacturer. The power distribution network of a printed circuit board (PCB) can be optimized using this model by choosing the number and the right values of decoupling capacitors as well as the size of power planes. The IC manufacturer may check out the autocompatibility of an IC and determine the number of power pins as well as the package to be used. As an example, jitter analysis of an integrated phase-locked-loop can be performed using ICEM. This paper demonstrates that this jitter can be predicted by simulation and that corrective solutions can be provided and checked out before implementation

This paper concentrates on some of these new challenges that designers must face in power delivery. We will discuss QUALCOMM's effort with EDA vendors to develop power distribution network (PDN) analysis flows in order to address the power delivery issues in 3DICs, and emphasize the necessity of a standard reduced power model (SRPM) to enable the 3D PDN analysis flows.

A charge-discharge optimization strategy considering the spatiotemporal distribution of electric vehicles and the operational safety of the power distribution network in the power-transportation coupling network

Due to aggressive storage capacity demands, multiple NAND Flash die are often stacked in a highly integrated, complex package system. As data-rate increases, bit time (UI) is shrinking, and accurate measurement of the data valid window and jitter become very important. Power distribution network (PDN) noise affects the overall system timing. The conventional way of PDN modeling approach in NAND Flash memory System level analysis, cannot accurately predict the system level jitter and deviates from the actual product level performance. In this paper, an accurate method for PDN-induced jitter analysis in NAND Flash system-level operation is described. Simulated PDN-induced jitter results are validated through characterization system and product level measurement jitter.

Distribution network reconfiguration is a very complex and large-scale combinatorial optimization problem. In network reconfiguration, whether an effective solution can be obtained is a key issue. Aiming at the problems in network reconstruction by traditional algorithm, such as long time required, more times of power flow calculation and high network loss, a network optimization design algorithm based on improved ant colony algorithm for high voltage power distribution network is proposed. After analyzing the operating characteristics of the high voltage power distribution network, the network topology of the high voltage power distribution network is described by constructing a hierarchical variable-structure distribution network model. A mathematical model of distribution network reconstruction considering the opportunity constraint with the minimum network loss as the objective function is established. The power flow distribution is calculated by using the pre-push back-generation method combined with the hierarchical structure of the distribution network. The maximum and minimum ant colony algorithm is introduced to improve the pheromone updating method of the traditional ant colony algorithm, and the search range is expanded, so that the algorithm can jump out of the local optimization trap to realize the accurate solution of the power distribution network reconstruction model. The experimental results show that compared with the current network reconstruction algorithm, the proposed algorithm requires less time for convergence, less power flow calculation, and lower network loss.

In terms of characteristics in urban active power distribution networks and trend of increasing penetration in distributed power, loss reduction problems in urban power distribution networks are studied in this paper. Considering not only random fluctuations of distributed power sources and loads, but also energy efficiency load management technology, air conditioning load, lighting load, and water heater load in controllable energy efficiency load are focused as research objects in this paper where its sensitivity to various influencing factors is analyzed. Moreover, mathematical models of controllable energy efficiency loads for air conditioning, lighting, and water heaters are established to implement mathematical modules for comprehensive damage reduction measures and improved harmony search algorithm is adopted. In addition, optimized load management is performed on the basis of it. Besides it, according to analysis and calculation of actual distribution network in certain city, correctness and superiority of research method are verified, and impact of optimized energy management technology on network loss of distribution network is analyzed as well.

Distributed generators (DGs) are nowadays most commonly used in distribution networks to meet the rising demand. The distribution network power flow is altered as more distributed generations are integrated with the distribution network. Analyzing and researching the network's power flow with distributed generation is an essential element of analyzing the distributed generation's influence on the networks. This study proposed new sites in the test network for the purpose of connecting DGs. Good results were obtained in improving the necessary network elements. Firstly, applying a Newton-Raphson method to measure the distribution network's power flow without distributed generations. Then the optimal power flow approach with DGs is set up based on many goals such as minimizing fuel cost, minimizing losses, voltage deviation, increasing efficiency, and the incremental fuel cost in the network appeared. Eventually, applying Particle Swarm to overcome the optimization problems. In MATLAB software environment and programing MATPOWER version 6.0, the simulation is evaluated and validated using the IEEE30 node method. The test results indicate that optimal power flow analysis with distributed generation will accomplish many networks aims and boost system economy.

In complex modern day electronic systems, far more time is spent in designing the boards, writing the software to drive and integrate the hardware, and other such system level issues, than is spent in designing any application-specific ICs that may be needed. Unfortunately, most of the research in computer-aided design has been focussed on the more glamorous ASIC design problem, as a result of which the design methodologies and tools at the system level are much more primitive than at the chip level. We have developed a design framework for application-specific systems, called SIERA, that addresses the higher level aspects of system design, including multichip design issues at the board-level, and hardware-software codesign and integration, in addition to the design of individual ASICs. SIERA allows rapid-prototyping of multiboard systems where the functionality is implemented using a mix of dedicated hardware modules and ASICs, as well as software running on programmable hardware modules. A key step in the design methodology provided by SIERA is that of generating the physical implementation of the system hardware from a description of the system architecture. The analogue of this problem at the chip level is referred to as silicon assembly or silicon compilation. In this paper we address this problem at the system level, and describe how the generation and interfacing of board-level modules, board-level physical design, simulation of custom boards, and the overall management of board design are handled in SIERA. While some of the problems could be solved by adapting or extending techniques from the existing ASIC design tools, others required new approaches. Case-studies of several real-life applications are also presented to demonstrate the effectiveness of the board-level physical design methodology embodied in SIERA compared to the traditional PCB design systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Clock distribution networks synchronize the flow of data signals between data paths, and the design of these networks can dramatically affect system wide performance and reliability. The field of clock distribution design can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom VLSI systems; 2) the automated synthesis of clock distribution networks with application to automated synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells, and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the specification of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described and summarized. Future trends are discussed. >

The DC distribution network based on the hybrid modular multilevel converter (MMC) has the ability of active current-limiting control, which plays an active role in fault clearing of distribution network. However, the fault characteristics of the DC distribution network become complicated because of the active current-limiting control. It brings new problems to the fault detection and judgment of relay protection. According to the structural features of the hybrid MMC, the start-up strategy and control objectives of the active current-limiting control are analyzed in this paper. The improvement suggestions are put forward to maintain the operational safety of the power grid, as well as meet the application requirements of the relay protection. Moreover, The characteristics of the short-circuit current of the DC distribution network are analyzed based on the active current-limiting control. Meanwhile, the influences on the relay protection are estimated. Finally, the effectiveness of the proposed current-limiting control strategy and the correctness of the fault characteristic analysis results are verified by simulation tests.

Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are reviewed, and compensating design techniques are discussed. The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated layout and synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the scheduling of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described the clock distribution networks of specific industrial circuits are surveyed and future trends are discussed.