Modeling and Analysis of Power Distribution Networks in 3-D ICs

This paper focuses on the modeling and analysis of different power distribution network (PDN) structures in 3D TSV ICs, including 3D full wave model and equivalent circuit model. In addition, a simplified equivalent circuit model of stacked PDN is proposed to analysis aspects influencing stacked PDN impedance, such as number of ground TSVs, number of TSV pairs and number of stacked layers. Analyses about how these aspects influencing total capacitance, inductance of stacked PDN and causing resonance in PDN self-impedance (Z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> ) are made in detail. What's more, power noise in different stacked PDN structures is calculated and analyzed in time domain to evaluate their power integrity features. Analysis in this paper can offer instructions for the design and analysis of on-chip PDN.

Accurate device parameters play critical roles in calculation and analysis of power distribution network (PDN). However, device parameters are always affected by the operating status and influenced by manual entry; besides, the distribution area of PDN is very wide with many points, which brings more challenges to PDN parameter identification. Most of the proposed algorithms recently assume that the parameters of PDN contribute in a nonlinear probability space and optimize parameters by the power flow model with a loss function. Although these algorithms can achieve satisfying results in PDN analysis, the relationship between the power flow model and loss functions remains unclear. In this paper, the outputs of the power flow model have been analyzed firstly by experimental data, which includes the head and end voltages, as well as active and reactive power on the low-voltage side. It is revealed that the loss functions used by current algorithms are not suitable and reasonable for power flow model in PDN calculation, which constitutes one of the main findings of this work. Subsequently, this work proposes four novel loss functions combined with genetic algorithm (GA) and Markov Chain Monte Carlo (MCMC) to identify PDN parameters. Compared with the published algorithms, our experimental results show that the loss function defined in this paper can achieve better and more stable performance with about two times lower in MAE, RMSE, and RMPE evaluation functions to identify PDN parameters.

With increasing design complexity, as well as continued scaling of supplies, the design and analysis of power distribution networks poses a difficult problem in modern IC design. We propose several closed-form solutions for power distribution network optimization and analysis which explicitly take into consideration the mesh topology. An RLC model for on-chip power distribution networks is presented for array and wire bonded integrated circuits including inter block decoupling capacitors and impedances. One of the more common design techniques for power distribution networks PDN is the determination of the impedance & supply noise. Current-mode technique is used. By using this current mode technique noise and impedance, voltage is analyzed.

A semiconductor industry has been encountered a memory bandwidth bottleneck toward a high density and high bandwidth system. In order to overcome those limitations, a 3D stacked high bandwidth memory (HBM) based on a through silicon via (TSV) and fine pitch interposer technology is lately introduced. By adopting this structure, thousands numbers of input/output (I/O) channels with a fine pitch can be integrated on HBM interposer which enables a terabyte/s bandwidth system. On the HBM interposer, significant numbers of I/O are integrated and they tend to operate at the same time which leads to severe simultaneous switching noise (SSN). When SSN occurs, the performance of system can be heavily degraded. Total SSN is strongly related to the self-noise and transfer-noise. In this point of view, a proper PDN design to manage transfer noise which is closely related to transfer-impedance must be taken into account. The analysis of power distribution network (PDN) impedance of HBM interposer must be performed since it generally affects power supply to the chips as well as signal integrity (SI). In this paper, HBM interposer with five layers is designed to analyze PDN. For PDN impedance analysis, Z-parameters depending on the various physical dimensions are simulated and compared. PDN impedance of HBM interposer is simulated and analyzed in the interest of frequency range dominated by interposer PDN. In order to suppress SSN, we suggest a metal-insulator-metal (MIM) de-cap scheme which can be commonly available for HBM interposer to reduce PDN impedance. Based on the designed physical dimension and material properties of HBM interposer, we successfully shows the suppression of SSN.

This paper proposes a locally implicit latency insertion method (LILIM), which is a suitable method for the fast simulation of an arbitrary shaped power distribution network (PDN) modeled by triangular meshes. First, an efficient modeling method based on triangular mesh is reviewed and we refer to the limitation of the LIM for the meshed PDN analysis. Next, in order to overcome the problem, we formulate the LILIM by combining the efficient modeling and the locally implicit schemes. Finally, the numerical results show that the LILIM is applicable and efficient for the simulation of the PDN analysis.

This paper concentrates on some of these new challenges that designers must face in power delivery. We will discuss QUALCOMM's effort with EDA vendors to develop power distribution network (PDN) analysis flows in order to address the power delivery issues in 3DICs, and emphasize the necessity of a standard reduced power model (SRPM) to enable the 3D PDN analysis flows.

An FPGA based electromagnetic transient analysis of power distribution network

Due to the high speed and system miniaturization trends in circuit design, predictive modeling of Power Distribution Network (PDN) in modern multilayered packages and boards becomes more and more important. To reduce design iterations due to signal and power integrity issues, the PDN model needs to be anticipated at early design stage, even if layout is not yet designed. Typical package PDNs consists of multiple layers of Power/Ground planes hence we can model it with a mesh of Multi-Conductor Transmission Lines (MCTLs). This paper presents a fast and efficient method based on unit MCTL calibration for a predictive modeling of different PDNs sizes.

This paper deals with the estimation of decoupling capacitance (decap) based on their power supply noise suppression and proper allocation of decap at the pre-layout level. By early prediction and allocation of decap at appropriate locations in the pre-layout circuit can only provide a better scope in optimizing noise, power and delay effects for the circuit. The novelty of our work lies in exhaustive estimation of power supply noise, followed by an algorithmic estimation and appropriate allocation of decap with an effort to keep noise, delay and power performance to its best. We choose 512-point FFT processor for our test circuit. To the best of our knowledge Power Distribution Network (PDN) analysis for execution time and noise suppression on FFT application cores is not available in related research works. By using our approach, power supply noise has been suppressed by 37.7%, delay and power consumption increases by 1.12% and 2.03% respectively at the pre-layout stage. This early predictions helps to create more accurate design at the layout stage and hence this work can serve as benchmark for PDN analysis.

Views Icon Views Article contents Figures & tables Video Audio Supplementary Data Peer Review Share Icon Share Twitter LinkedIn Tools Icon Tools Get Permissions Cite Icon Cite Search Site Citation Bruce Archambeault, Ketan Shringarpure, Jun Fan, Sam Connor; Fast and Accurate Multi-Layer PDN Analysis for Power Integrity and EMC. International Symposium on Microelectronics 1 January 2010; 2010 (1): 000566–000571. doi: https://doi.org/10.4071/isom-2010-WP2-Paper1 Download citation file: Ris (Zotero) Reference Manager EasyBib Bookends Mendeley Papers EndNote RefWorks BibTex toolbar search Search Dropdown Menu nav search search input Search input auto suggest Search

This paper discusses the electrical characteristics of power distribution networks (PDNs) in 3DICs on both system and chip level. In the system-level analysis the global resonance effects in 3D PDNs are highlighted. For chip-level analysis, detailed metal-layer-based power grid model is proposed for the first time for 3D PDNs. With the detailed power grid model, local resonance effects that are unique to 3D PDNs are revealed. The spatial and temporal impacts of distributed current sources on the time-domain noise of 3D PDNs are also explored based on the multi-source worst-case noise calculation algorithm. Simulation results demonstrate the “Rogue Wave” phenomenon in 3D PDNs.

This paper presents the analysis of power distribution network impedance and loop inductance of irregular parallel-plane structures and multi-slots plane-pair structures by using the plane-pair partial element equivalent circuit method(PPP). The influence of slot area occupancy rate (AOR) on impedance and loop inductance is investigated for various structures. The test structure is designed and fabricated to validate the influence of AOR on impedance and loop inductance of the PDN. The simulation and measurement of the structure impedance are performed up to 10GHz, and the good agreement are obtained between the simulation and the experiment.

This work presents an analysis of the performance of surge suppression devices that currently are applied in power distribution network. Based on the Transmission Lines Method - TLM, numerical models for these devices have been created and their computational implementation made by using MATLAB™ codes. These models were simulated with some types of power surges and a comparison of results is made with measurements of actual devices and other methods of simulation obtained in the literature for verifying the efficiency of the proposed methodology. Also, it is presented some advantages over other methods for analysis of power distribution network, subjected to the effects of fast transients.

In this paper, we design and analyze the hierarchical power distribution network (PDN) for full wafer scale chip (FWSC) module. With its high bandwidth and low latency, FWSC has been considered a promising solution in the artificial intelligence (AI) processor market. However, the huge size of FWSC inevitably leads to long current paths and high impedance that consequently cause large IR drop and power/ground noise. In an effort to overcome these issues, the hierarchical PDN of FWSC module is designed in a 3D structure that allows direct interconnection from PCB to chip to minimize the current path. Although there are several studies related to PDN design for FWSC module, they conducted limited analysis on a specific PDN only. We design the hierarchical PDN for FWSC module composed of PCB PDN, multi-array silicone rubber socket (SRS)-based PDN, multi-array through wafer via (TWV)-based PDN, and on-chip PDN. Each PDN component was modeled into equivalent circuit models. Then, we fully analyzed the overall hierarchical PDN impedance in the frequency domain.

As the complexity of a modern microprocessor increases rapidly, the methods of testing/debug take up increasing silicon area and create a cumbersome routing problem. The core power distribution network (PDN) of a microprocessor supplies power to a majority of underlying circuits. In this paper, we propose to explore use of the PDN in a microprocessor as a communication channel for test/debug purposes. Although, there are some common characteristics with power line communications (PLC) over power grid in a residential network, PLC over a PDN is very different in channel characteristics, tolerance to voltage fluctuations and noise characteristics. Further, decoupling capacitors attached to the package and the PDN of a microprocessor makes the PDN a bulky low pass filter. However, it is well known that the parasitic inductance of a decoupling capacitor is more significant beyond the self resonant frequency, and our measurements on an Intel microprocessor indicates that the low pass filter becomes leaky at higher frequencies beyond 1 GHz. In this work, measurements are used to model the PDN of a microprocessor as a communication channel and estimate the path loss characteristics as well as the channel impulse response. Link budget is calculated for the proposed communication system and receiver design considerations are derived. Measurement results and power supply noise analysis indicate that the use of jitter-robust pulse shapes, spread-spectrum techniques and strong coding would be required to communicate reliably over the PDN of a microprocessor.