Fast transient analysis of power distribution network modeled by unstructured meshes by using locally implicit latency insertion method

This paper focuses on the modeling and analysis of different power distribution network (PDN) structures in 3D TSV ICs, including 3D full wave model and equivalent circuit model. In addition, a simplified equivalent circuit model of stacked PDN is proposed to analysis aspects influencing stacked PDN impedance, such as number of ground TSVs, number of TSV pairs and number of stacked layers. Analyses about how these aspects influencing total capacitance, inductance of stacked PDN and causing resonance in PDN self-impedance (Z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> ) are made in detail. What's more, power noise in different stacked PDN structures is calculated and analyzed in time domain to evaluate their power integrity features. Analysis in this paper can offer instructions for the design and analysis of on-chip PDN.

This paper addresses the modeling and analysis problems for power distribution networks (PDNs) in 3-D ICs. An on-chip distributed model is proposed for 3-D power grids, in which the details of metal layers are considered. The distributed model is demonstrated to be essential to identifying the unique noise behavior of 3-D PDNs. A lumped model is proposed based on the distributed model. The lumped model features the connection impedance between tiers and is proven to be useful for designers to understand the global effects of 3-D PDNs. Based on the models, an analysis flow is designed for 3-D PDNs in both frequency domain and time domain. With the analysis flow, the electrical characteristics of 3-D PDNs are studied systematically for the first time. The frequency-domain analysis identifies the global and local resonance phenomena in 3-D PDNs that are distinct from those in 2-D PDNs. The physical mechanisms behind the resonance phenomena are investigated. The time-domain analysis predicts the worst-case supply noise based on distributed current constraints. The “Rogue Wave” concept is introduced to explain the spatial and temporal relations of the worst-case on-chip noise responses in 3-D PDNs.

Accurate device parameters play critical roles in calculation and analysis of power distribution network (PDN). However, device parameters are always affected by the operating status and influenced by manual entry; besides, the distribution area of PDN is very wide with many points, which brings more challenges to PDN parameter identification. Most of the proposed algorithms recently assume that the parameters of PDN contribute in a nonlinear probability space and optimize parameters by the power flow model with a loss function. Although these algorithms can achieve satisfying results in PDN analysis, the relationship between the power flow model and loss functions remains unclear. In this paper, the outputs of the power flow model have been analyzed firstly by experimental data, which includes the head and end voltages, as well as active and reactive power on the low-voltage side. It is revealed that the loss functions used by current algorithms are not suitable and reasonable for power flow model in PDN calculation, which constitutes one of the main findings of this work. Subsequently, this work proposes four novel loss functions combined with genetic algorithm (GA) and Markov Chain Monte Carlo (MCMC) to identify PDN parameters. Compared with the published algorithms, our experimental results show that the loss function defined in this paper can achieve better and more stable performance with about two times lower in MAE, RMSE, and RMPE evaluation functions to identify PDN parameters.

An FPGA based electromagnetic transient analysis of power distribution network

A semiconductor industry has been encountered a memory bandwidth bottleneck toward a high density and high bandwidth system. In order to overcome those limitations, a 3D stacked high bandwidth memory (HBM) based on a through silicon via (TSV) and fine pitch interposer technology is lately introduced. By adopting this structure, thousands numbers of input/output (I/O) channels with a fine pitch can be integrated on HBM interposer which enables a terabyte/s bandwidth system. On the HBM interposer, significant numbers of I/O are integrated and they tend to operate at the same time which leads to severe simultaneous switching noise (SSN). When SSN occurs, the performance of system can be heavily degraded. Total SSN is strongly related to the self-noise and transfer-noise. In this point of view, a proper PDN design to manage transfer noise which is closely related to transfer-impedance must be taken into account. The analysis of power distribution network (PDN) impedance of HBM interposer must be performed since it generally affects power supply to the chips as well as signal integrity (SI). In this paper, HBM interposer with five layers is designed to analyze PDN. For PDN impedance analysis, Z-parameters depending on the various physical dimensions are simulated and compared. PDN impedance of HBM interposer is simulated and analyzed in the interest of frequency range dominated by interposer PDN. In order to suppress SSN, we suggest a metal-insulator-metal (MIM) de-cap scheme which can be commonly available for HBM interposer to reduce PDN impedance. Based on the designed physical dimension and material properties of HBM interposer, we successfully shows the suppression of SSN.

Views Icon Views Article contents Figures & tables Video Audio Supplementary Data Peer Review Share Icon Share Twitter LinkedIn Tools Icon Tools Get Permissions Cite Icon Cite Search Site Citation Bruce Archambeault, Ketan Shringarpure, Jun Fan, Sam Connor; Fast and Accurate Multi-Layer PDN Analysis for Power Integrity and EMC. International Symposium on Microelectronics 1 January 2010; 2010 (1): 000566–000571. doi: https://doi.org/10.4071/isom-2010-WP2-Paper1 Download citation file: Ris (Zotero) Reference Manager EasyBib Bookends Mendeley Papers EndNote RefWorks BibTex toolbar search Search Dropdown Menu nav search search input Search input auto suggest Search

This paper concentrates on some of these new challenges that designers must face in power delivery. We will discuss QUALCOMM's effort with EDA vendors to develop power distribution network (PDN) analysis flows in order to address the power delivery issues in 3DICs, and emphasize the necessity of a standard reduced power model (SRPM) to enable the 3D PDN analysis flows.

With increasing design complexity, as well as continued scaling of supplies, the design and analysis of power distribution networks poses a difficult problem in modern IC design. We propose several closed-form solutions for power distribution network optimization and analysis which explicitly take into consideration the mesh topology. An RLC model for on-chip power distribution networks is presented for array and wire bonded integrated circuits including inter block decoupling capacitors and impedances. One of the more common design techniques for power distribution networks PDN is the determination of the impedance & supply noise. Current-mode technique is used. By using this current mode technique noise and impedance, voltage is analyzed.

This paper presents the analysis of power distribution network impedance and loop inductance of irregular parallel-plane structures and multi-slots plane-pair structures by using the plane-pair partial element equivalent circuit method(PPP). The influence of slot area occupancy rate (AOR) on impedance and loop inductance is investigated for various structures. The test structure is designed and fabricated to validate the influence of AOR on impedance and loop inductance of the PDN. The simulation and measurement of the structure impedance are performed up to 10GHz, and the good agreement are obtained between the simulation and the experiment.

This paper deals with the estimation of decoupling capacitance (decap) based on their power supply noise suppression and proper allocation of decap at the pre-layout level. By early prediction and allocation of decap at appropriate locations in the pre-layout circuit can only provide a better scope in optimizing noise, power and delay effects for the circuit. The novelty of our work lies in exhaustive estimation of power supply noise, followed by an algorithmic estimation and appropriate allocation of decap with an effort to keep noise, delay and power performance to its best. We choose 512-point FFT processor for our test circuit. To the best of our knowledge Power Distribution Network (PDN) analysis for execution time and noise suppression on FFT application cores is not available in related research works. By using our approach, power supply noise has been suppressed by 37.7%, delay and power consumption increases by 1.12% and 2.03% respectively at the pre-layout stage. This early predictions helps to create more accurate design at the layout stage and hence this work can serve as benchmark for PDN analysis.

This work presents an analysis of the performance of surge suppression devices that currently are applied in power distribution network. Based on the Transmission Lines Method - TLM, numerical models for these devices have been created and their computational implementation made by using MATLAB™ codes. These models were simulated with some types of power surges and a comparison of results is made with measurements of actual devices and other methods of simulation obtained in the literature for verifying the efficiency of the proposed methodology. Also, it is presented some advantages over other methods for analysis of power distribution network, subjected to the effects of fast transients.

This paper presents the implementation of a new LIM-SPICE simulator. The latency insertion method (LIM) is improved and integrated into SPICE as an accelerating option. Since LIM has linear computational complexity and is substantially faster than SPICE, the new LIM-SPICE simulator can simulate large linear networks with substantially higher speed within the SPICE simulation framework. In addition, mutual inductance between branches are handled by utilizing a K matrix formulation.

The locally implicit leapfrog scheme has been proposed as one of the signal/power integrity (SI/PI) circuit simulation techniques of an arbitrary shaped power distribution network (PDN) modeled by triangular meshes. This method can perform transient analysis several times faster than the explicit leapfrog scheme by employing a locally implicit scheme instead of the globally explicit leapfrog scheme. In this paper, we describe the nonlinear circuit simulation technique of the locally implicit leapfrog scheme for fast simulation of the PDN modeled by triangle meshes. First, the modeling method by using the triangular meshes and the formulation of the locally implicit leapfrog scheme. Next, we describe the nonlinear circuit simulation technique of the locally implicit leapfrog scheme. Finally, some numerical results are shown, and it is confirmed that the proposed technique is useful and efficient for the fast simulation of the PDN including nonlinear circuit modeled by triangle meshes.

Review on vulnerability analysis of power distribution network

EVs are recognized as distributed loads and power sources with random motion characteristics in the power distribution networks (PDN); therefore, they serve as connecting points for the distribution network and transportation network (PDN-TN), and have significant impact on the stability and reliability of the routine operation of the coupled networks. In order to guarantee the safe operation of PDN-TN, it is necessary to evaluate the reliability of this coupled network. In this paper, the trip chaining theory is applied to describe the travel plan of EVs, and semi-dynamic flow allocation (SDTA) method is adopted to propose a simulation calculation method of energy flow between two networks based on user equalization (UE) criterion. The new reliability evaluation index for energy flow between the coupled networks is further proposed to better evaluate the reliability. Taking into account the daily trip characteristics of EVs, vehicles types, and charging modes, a coupled network reliability evaluation method based on sequential Monte Carlo simulation is put forward. Finally, the practicability of the proposed method is verified by an IEEE-RBTS BUS-6 test system and a 12-node transportation network.