Fast Online Set Intersection for Network Processing on FPGA

Wireless communication exhibits the highest energy consumption in wireless sensor networks nodes. Due to their limited energy supply from batteries, the low power VLSI designs have become inevitable part of today's wireless devices. Power has become a burning issue in VLSI design. In modern integrated circuits, the power consumed by clocking gradually takes a dominant part. Reducing the power consumption not only can enhance battery life but also can avoid the overheating problem. By employing a more appropriate processing element, the power consumption is significantly reduced. In this paper the novel method for low power design is achieved by using Multi-Bit Flip-Flop Merging (MBFM) technique for on-the-node data processing in wireless sensor networks using Parallel Prefix Operations (PPO) and data locality in hardware. Besides power reduction the objective of minimizing area and delay is also considered.

Multicore Processors and Systems provides a comprehensive overview of emerging multicore processors and systems. It covers technology trends affecting multicores, multicore architecture innovations, multicore software innovations, and case studies of state-of-the-art commercial multicore systems. A cross-cutting theme of the book is the challenges associated with scaling up multicore systems to hundreds of cores. The book provides an overview of significant developments in the architectures for multicore processors and systems. It includes chapters on fundamental requirements for multicore systems, including processing, memory systems, and interconnect. It also includes several case studies on commercial multicore systems that have recently been developed and deployed across multiple application domains. The architecture chapters focus on innovative multicore execution models as well as infrastructure for multicores, including memory systems and on-chip interconnections. The case studies examine multicore implementations across different application domains, including general purpose, server, media/broadband, network processing, and signal processing. Multicore Processors and Systems is the first book that focuses solely on multicore processors and systems, and in particular on the unique technology implications, architectures, and implementations. The book has contributing authors that are from both the academic and industrial communities.

In most network processors (NP), multiple CPU cores are employed to exploit packet level parallelism, where high processing resource utilization and within-flow packet order preservation are two fundamental design targets. However, while many researches are only focused on the first one, the second has not been solved perfectly. In this paper, a high-speed NP architecture is proposed to handle both of the two issues simultaneously, where a centralized state controller with hardware flow chains is employed to schedule the CPU cores fairly and to transmit the packets orderly. We also introduce local memory to increase CPU utilization as well as to store packets that can't be sent out immediately due to flow constraints. We implement the NP prototype with an FPGA, upon which a series of experiments are carried out, and the results indicate that it can achieve both of the two goals perfectly.

SummaryMulticore network processors have been playing an increasingly important role in computational processes, which emphasize on scalability and parallelism of the systems, in distributed environments especially in Internet‐based delay‐sensitive applications. It is an important but unsolved issue, however, to efficiently schedule tasks in network processors with multicore and multithread for improving the system throughput as much as possible. Profiling can gather runtime environment information and guide the compiler to optimize programs through scheduling tasks based on the runtime context. This paper proposes a profiling‐based task scheduling approach, targeting on improving the throughput of multicore network processor (Intel IXP) systems in the balanced pipeline way. In this work, we investigate a profiling‐based task scheduling framework, a task scheduling algorithm, and a set of performance models. Our task allocation scheme maps tasks onto the pipeline architecture and multiple threads of network processors in parallel, which incorporates the profiling context and global thread refinement. We evaluate our task scheduling algorithm by implementing representative network applications on the Intel IXP network processor. Experimental results demonstrate that our algorithm is able to schedule tasks in a balanced pipeline fashion and achieve the high throughput and data transmission rate. Copyright © 2012 John Wiley & Sons, Ltd.

Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multi-threading and heterogeneous multiprocessing, which usually requires programmers to manually create multiple tasks and map these tasks onto different processing elements. This paper addresses the problem of automating task creation and mapping of network applications onto the underlying hardware to maximize their throughput. We propose a throughput cost model to guide the task creation and mapping with the objective of both minimizing the number of stages in the processing pipeline and maximizing the average throughput of the slowest task simultaneously. The average throughput is modeled by taking communication cost, computation cost, memory access latency and synchronization cost into account. We envision that programmers write small functions for network applications, such that we use grouping and duplication to construct tasks from the functions. The optimal solution of creating tasks from m functions and mapping them to n processors is an NP-hard problem. Therefore, we present a practical and efficient heuristic algorithm with an O((n + m)m) complexity and show that the obtained solutions produce excellent performance for typical network applications. The entire framework has been implemented in the Open Research Compiler (ORC) adapted to compile network applications written in a domain-specific dataflow language. Experimental results show that the code produced by our compiler can achieve the 100% throughput on the OC-48 input line rate. OC-48 is a fiber optic connection that can handle a 2.488Gbps connection speeds, which is what our targeted hardware was designed for. We also demonstrate the importance of good creation and mapping choices on achieving high throughput. Furthermore, we show that reducing communication cost and efficient resource management are the most important factors for maximizing throughput on the Intel IXP network processors.KeywordsNetwork ProcessorsThroughputIntel IXPDataflow ProgrammingTask Creation and Mapping

Today, designers of network processors strive to keep the packet reception and transmission orders identical, and therefore avoid any possible out-of-order transmission. However, the development of new features in advanced network processors has resulted in increasingly parallel architectures and increasingly heterogeneous packet processing times, leading to large reordering delays. In this paper, we introduce novel scalable scheduling algorithms for preserving flow order in parallel multi-core network processors. We show how these algorithms can reduce reordering delay while adapting to any load-balancing algorithm and keeping a low implementation complexity overhead. To do so, we use the observation that all packets in a given flow have similar processing requirements and can be described with a constant number of logical processing phases. We further define three possible knowledge frameworks of the time when a network processor learns about these logical phases, and deduce appropriate algorithms for each of these frameworks. Finally, we model our proposed algorithms and simulate them under both synthetic traffic and real-life traces, and show that they significantly outperform past approaches.

The number of processors is increasing, but the usefulness of parallel computation is not better leveraged due to the inflexibility of design and implementation for multiprocessor embedded system applications. A higher level abstraction (i.e., a parallel programming framework) can ease the programmers to define parallelism for tasks in an application but designers still face the complexity of mapping high-level requirements to the syntax and semantics of a parallel programming interface. Nevertheless, embedded system applications execute various periodic tasks that are carried out repeatedly within a certain time interval and these tasks may be able to run in parallel to utilize the system efficiently. Therefore, in this paper, we propose a parallel loop-based task construct approach to automate the design process of embedded system applications from AADL models for a parallel programming framework. To illustrate the applicability of our mechanism, we use a well-known parallel programming interface called OpenMP to demonstrate the automation process in mapping tasks over multiple processor cores. To ensure meeting high-level requirements of embedded system applications, we analyze the existing OpenMP scheduling mechanisms and propose a layer of adaptation. We show that our proposed adaptation layer facilitates a tighter execution time bound for time-sensitive tasks or a better throughput for tasks that require higher quality of service. Thus, the proposed design automation framework is applicable for a variety of applications with different quality of service (QoS) requirements preserved at the lower level.

With the development of high-speed network, the demand of high performance network processing keeps rising. Multi-core network processors (NPs), specially designed for network processing, are widely used in a variety of network applications to achieve high throughput. However, when using TCP stack of Linux which runs on the multi-core network processor to transmit data across the network, the performance is far from optimal. In this paper, a multi-path reliable data transfer (MPRDT) system based on multi-core network processors is proposed to get higher performance. The proposed system implements a UDP-based reliable data transfer stack in the real-time operating system (RTOS) of the multi-core network processors. Furthermore, a multi-path method is applied to enable the system to manage multi-path connections through different interfaces to different receiver ends, taking full use of the network interfaces and bandwidth resources. The experimental results indicate that the MPRDT can manage multipath connections properly and get higher throughput with less consumption of CPU resource than the Linux scheme.

Network processors (NPs) typically contain multiple concurrent processing cores. State-of-the-art programming techniques for NPs are invariably low-level, requiring programmers to partition code into concurrent tasks early in the design process. This results in programs that are hard to maintain and hard to port to alternative architectures. This paper presents a new approach in which a high-level program is separated from its partitioning into concurrent tasks. Designers write their programs in a high-level, domain-specific, architecturally-neutral language, but also provide a separate Architecture Mapping Script (AMS). An AMS specifies semantics-preserving transformations that are applied to the program to re-arrange it into a set of tasks appropriate for execution on a particular target architecture. We (i) describe three such transformations: pipeline introduction, pipeline elimination and queue multiplexing; and (ii) specify when each can be safely applied.As a case study we describe an IP packet-forwarder and present an AMS script that partitions it into a form capable of running at 3Gb/s on an Intel IXP2400 Network Processor.KeywordsGlobal VariableConcurrent TaskConcurrent ProgramSource ProgramTarget ArchitectureThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip

Chip multiprocessor designs are the most common types of architectures seen in Network Processors. As the Network Processors are used to implement increasingly complicated applications, task distribution among the cores is becoming an important problem. In this paper, we propose a new task allocation scheme for such architectures. This scheme relies on the inherent modular nature of the networking applications and intelligently distributes modules among different execution cores. Additionally, we selectively replicate modules to parallelize execution of tasks having longer processing time. We have developed a technique that uses the probability distribution of the execution times of different modules in the networking applications. The proposed schemes result in resource utilization of up to 95%, 89%, and 84% on average for the processors with 2, 4, and 8 cores, respectively. The schemes are highly scalable and can improve the throughput by 6.72 times for 8 core processors, aggregated over four representative applications. The combination of selective replication of modules and variation-aware task allocation result in up to 12.5% (9.9% on average) performance improvement as compared to a scheme based on just mean processing time.

This paper describes a compilation technique used to accelerate dataflow computations, common in deep neural network computing, onto Coarse Grained Reconfigurable Array (CGRA) architectures. This technique has been demonstrated to automatically compile dataflow programs onto a commercial massively parallel CGRA-based dataflow processor (DPU) containing 16000 processing elements. The DPU architecture overcomes the von Neumann bottleneck by spatially flowing and reusing data from local memories, and provides higher computation efficiency compared to temporal parallel architectures such as GPUs and multi-core CPUs. However, existing software development tools for CGRAs are limited to compiling domain specific programs to processing elements with uniform structures, and are not effective on complex micro architectures where latencies of memory access vary in a nontrivial fashion depending on data locality. A primary contribution of this paper is to provide a general algorithm that can compile general dataflow graphs, and can efficiently utilize processing elements with rich micro-architectural features such as complex instructions, multi-precision data paths, local memories, register files, switches etc. Another contribution is a uniquely innovative application of Boolean Satisfiability to formally solve this complex, and irregular optimization problem and produce high-quality results comparable to hand-written assembly code produced by human experts. A third contribution is an adaptive windowing algorithm that harnesses the complexity of the SAT-based approach and delivers a scalable and robust solution.

Nowadays, network operators' amenities are populated with a huge amount of proprietary hardware devices for carrying out their core tasks. In this context, industry and academia have turned an eye to virtualization techniques to mitigate those effects and maximize potential earnings. Network Function Virtualization (NFV) aims to transform future network architectures by exploiting standard IT virtualization technology to consolidate a variety of network processing elements onto standard commodity servers. This work assesses the feasibility of moving high-performance network processing tasks to a virtualized environment. For such purpose, we analyse the possible configurations that allow feeding the network traffic to applications running inside virtual machines. We have given a set of guidelines that allow exploiting the functionality of generating virtual network functions, enabling a set of interesting scenarios and testing their performance bounds. We also developed HPCAPvf, a counterpart of HPCAP for virtual environments, and made it available under a GPL license.

This paper proposes a hierarchical photoelectric network with an electrical and optical interleaved packet switching scheme for low latency as well as high throughput in high-performance computing systems. To reduce the overhead of electrical plane or preconfiguration structure adopted in conventional optical networks, what we believe to be a novel electrical switch architecture is proposed to perform route computation for both electrical and optical switches simultaneously. Moreover, a fine-grained flow control mechanism is presented to prevent packet drop and improve link utilization. Based on the developed discrete-event simulator with non-permutation, bit permutation, and digit permutation traffic patterns, experimental results show that the proposed network achieves latency and throughput improvements from 2.3% to 17.3% and − 0.01 % to 4.7%, respectively. Furthermore, we extend the proposed network with a multilayer electrical and optical interleaved scheme. The multilayer interleaved scheme achieves up to 32.5% latency reduction and 9.6% throughput improvement.

The rapid expansion of Internet of Things (IoT) devices has highlighted the shortcomings of traditional centralized identity management systems, which often suffer from single points of failure, high latency, and limited scalability. These challenges are particularly significant in IoT environments with limited resources, where secure and efficient identity management is crucial for real-time data processing and decision-making. This paper introduces a consortium blockchain-based IoT identity management system enhanced by fog computing. By utilizing blockchain’s decentralized and tamper-resistant features, the system secures identity management, while fog computing minimizes latency by processing data closer to its source. Our system is designed to scale effectively, even in densely populated IoT deployments, while maintaining low energy consumption and high throughput. Simulation results show notable reductions in latency and improvements in throughput, with the system achieving an average latency of 175.15 ms for registration operations with a 0.35 MB payload. The system’s robustness is further demonstrated by its resilience to common IoT security threats, such as man-in-the-middle attacks and node compromise. Key contributions include the innovative integration of blockchain and fog computing, enhanced scalability and efficiency, improved security through decentralized identity management, and adaptability to emerging technologies like quantum-resistant cryptography.