Multicore Processors and Systems

In this paper, we analyze the effect of interconnect on multi-core processors and have proposed a novel highly scalable on-chip interconnection mechanism for multi-core processors. As the number of cores increases, traditional on-chip interconnect like bus and crossbar proves to be low in efficiency as well as suffer from poor scalability. In order to get rid of the scalability and efficiency issues in these traditional interconnects, ring based design has been proposed. But with the steady growth in number of cores have rendered the ring interconnect too infeasible. Thus, novel interconnect designs are proposed for the future multi-core processors for enhancement in the scalability. In this paper, we analyze and compare the interconnect of two existing multi-core processors named Multi-core Processor with Internal Network(MPIN) and Mult-core processor with Ring Network(MPRN). We have also proposed a highly scalable and efficient interconnect named as fabricated Implant in Interconnect for multi-core processors. The placement of cores and cache in a network is proved to be highly crucial for system performance. The benchmark results are presented by using a full system simulator. Results show that, by using the proposed on-chip interconnect, compared with the MPIN and MPRN, the execution time are significantly reduced for three applications.KeywordsMulti-core ProcessorPerformance analysisInterconnectCache Dependency

Signal integrity and associated optimization techniques in power delivery network for multi-core processors, whether powered by a single converter or several power converters, are discussed. The high integration of the multi-core processors on a single die makes chipset's sensitivity to crosstalk noise more likely. Several power converters in a multi-core processor system could improve energy efficiency and dynamic performance among others. However, this paper focuses on how several power converters can be used to achieve over 60dB of crosstalk noise isolation. Crosstalk noise can be reduced by dedicating a power converter for each processor core (or more) and placing the power converters between the processors cores.

General-purpose multicore processors are being accepted in all segments of the industry, including signal processing and embedded space, as the need for more performance and general-purpose programmability has grown. Parallel processing increases performance by adding more parallel resources while maintaining manageable power characteristics. The implementations of multicore processors are numerous and diverse. Designs range from conventional multiprocessor machines to designs that consist of a "sea" of programmable arithmetic logic units (ALUs). In this article, we cover some of the attributes common to all multicore processor implementations and illustrate these attributes with current and future commercial multicore designs. The characteristics we focus on are application domain, power/performance, processing elements, memory system, and accelerators/integrated peripherals.

The microprocessor industry is rapidly moving towards chip multi-processors (CMPs), commonly referred to as multi-core processors, where multiple cores can independently execute different threads. This change in computer architecture requires corresponding design modifications in programming paradigms, including grid middleware tools, to harness the opportunities presented by multi-core processors. Naive implementations of grid middleware on multi-core systems can severely impact performance because of limitations of shared bus bandwidth, cache size and coherency, and communication between threads. The goal of developing an optimized multi-threaded grid middleware for emerging multi-core processors will be realized only if researchers and developers have access to an in-depth analysis of the impact of several low level microarchitectural parameters on performance. None of the current grid simulators and emulators provide feedback at the microarchitectural level, which is essential for such an analysis. We describe the initial design and implementation of an emulation framework, Multi-core Grid (McGrid), to analyze and provide insightful feedback on the performance limitations, bottlenecks, and optimization opportunities for grid middleware on multi-core systems. We describe early performance results of emulating the processing of some representative XML based grid documents on multi-core nodes using the McGrid framework.

Nowadays, convolutional neural networks are among the most widely used types of deep learning networks thanks to their usefulness in many application domains. There are many efforts to find methods to increase their training and inference performance and efficiency. One of the most widely used technique to implement convolution consists of flattening tensors into 2D matrices and carrying out the operation through a matrix-matrix multiplication routine, which has highly optimized implementations in high-performance libraries. However, this kind of approach uses extra time and memory to transform and store the tensors involved. For this reason, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">direct convolution</i> is becoming increasingly popular. Direct convolution can be implemented as a series of nested loops iterating over tensor dimensions and it does not require extra memory. In this work, we evaluate on various multi-core CPUs the performance and scalability effects deriving from different parallelization strategies, loop organizations, and SIMD-vectorization approaches with different compilers in relation with architectural aspects. We discuss each parameter thoroughly and distill our findings in a set of heuristics that can be used to quickly achieve a high-performance implementation in accordance to the underlying hardware and the characteristics of the convolutional layer at hand. By adopting a per-layer approach, we increase performance up to 60-70% compared to a static implementation for all the layers. Moreover, our results are comparable, or even better (up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.67\times $ </tex-math></inline-formula> speedup) than matrix-matrix multiplication-based convolution in a multi-core system.

SummaryMulticore network processors have been playing an increasingly important role in computational processes, which emphasize on scalability and parallelism of the systems, in distributed environments especially in Internet‐based delay‐sensitive applications. It is an important but unsolved issue, however, to efficiently schedule tasks in network processors with multicore and multithread for improving the system throughput as much as possible. Profiling can gather runtime environment information and guide the compiler to optimize programs through scheduling tasks based on the runtime context. This paper proposes a profiling‐based task scheduling approach, targeting on improving the throughput of multicore network processor (Intel IXP) systems in the balanced pipeline way. In this work, we investigate a profiling‐based task scheduling framework, a task scheduling algorithm, and a set of performance models. Our task allocation scheme maps tasks onto the pipeline architecture and multiple threads of network processors in parallel, which incorporates the profiling context and global thread refinement. We evaluate our task scheduling algorithm by implementing representative network applications on the Intel IXP network processor. Experimental results demonstrate that our algorithm is able to schedule tasks in a balanced pipeline fashion and achieve the high throughput and data transmission rate. Copyright © 2012 John Wiley &amp; Sons, Ltd.

Our investigation into architectural support for networking tasks began in late 1998, and it began with something of a coincidence. Fiuczynski was an active graduate student participant in the SPIN project at UW [2,3]. He had been writing a SPIN driver for a high-speed network interface card (NIC), and visited Crowley (at the time, a graduate student investigating the relationships between processor & memory architectures and desktop computer applications [4]) one afternoon to discuss the NIC's processor. Had either Fiuczynksi or Crowley been out of the office on that particular day, it is not clear that this collaboration would have emerged. As it happened, both were in the office that day and the NIC processor was very interesting: a dual-core MIPS-like processor built specifically for the NIC. In ensuing discussions, it became clear that-despite the simplicity of its instruction set and microarchitecture-the NIC processor was as a whole more interesting than the much larger and complex x86 processor of the host system. It was more interesting because, as a dual-core processor, it was different and in no way an incremental improvement upon the deeply pipelined CPUs that dominated computing at the time. (They still dominate PCs and servers, of course, but mobile, graphics and embedded chips represent a huge swath of relevant computing platforms today.) It represented evidence of a combination of commercial and technical justification for designing a new and different processor to handle networking tasks.

Packet classification matches a packet header against the predefined rules in a rule set, it is a kernel function that has been studied for decades. A recent trend in packet classification is to match a large number of packet header fields. For example, the flow table lookup in Software Defined Networking (SDN) requires 15 fields of the packet header to be examined. Another trend in packet classification is to use software-based solutions employing multi-core general purpose processors and virtual machines. Although packet classification has been widely studied, most existing solutions on multi-core systems target the classic 5-field packet classification, their performance cannot be easily scaled up for a larger number of packet header fields. In this paper, we propose a decomposition-based packet classification approach, it supports large rule sets consisting of a large number of packet header fields. We first use range-tree and hashing to search each field of the input packet header individually in parallel. The partial results from all the fields are represented by bit vectors, they are merged in parallel to produce the final packet header match. We also balance the search and merge latencies, and employ software pipelining to further enhance the overall performance. We implement our approach on state-of-the-art multi-core processors, we evaluate its performance with respect to throughput and latency for rule set size ranging from 1K to 32K. Experimental results show that, for a 32K rule set, our algorithms can achieve an average processing latency of 2000 ns per packet and an overall throughput of 30 million packets per second on a state-of-the-art 16-core platform.

At the operating system level, multi-core and multiprocessor SoC(MPSoC) started a new computing era but brought various twofold scheduling challenges in current developed thermal aware algorithms for multi-core processors. An offline thermal aware scheduling algorithm is proposed for improvement in multi core embedded system in case of energy, reliability as well as performance of a multi core system has been introduced. Embedded systems are increasing at much rapid speed than ever before. The temperature of a multi-core processor is managed and measured by the hardware management system due to shrinking of chip size power densities are increasing due to this increase in the temperature of chip occurs that reduces the processor's speed in multi-core embedded system. High peak temperature on chip adversely affects the life span of chip. Task migration is a common technique to avoid peak temperature values in multi core system. Those tasks have been migrated in a multi core system which produces more heat to such individual core that has less temperature. The proposed technique also considers other thermal problems which affects the reliability and performance of multi-core system. In this research, a suitable scheduling mechanism assign tasks to the core that has less temperature by considering power and performance of the multi core system. This scheduling technique migrate load on the cores that is far away from the core reaches threshold temperature. For attaining stability in temperature among multiple cores results are evaluated by comparing different task migration techniques which are introduced previously. All types of hot and cold tasks are considered to predict accurate temperature by using thermal history. The scheduling policy attains maximum efficiency in terms of energy by considering only those cores that are executing some tasks in highest energy state such as running state while considering all other cores in lowest energy state such as sleep or a deep sleep mode. The simulation results shows that the proposed technique reduces almost 5°C temperature at 10% utilization and works efficiently when least number of tasks is in running state. The proposed technique has the ability to schedule more tasks to make a slower and energy efficient processor to control and manage the thermal effects on chip and also mange the processor energy consumption.

Embedded system design is the core for many time constraint application designs like avionics and railways. These systems employ multi core architecture for faster and time critical applications. Use of multi cores as the processing part is ever challenging due to the complexities involved in their designs, memory architecture, issues related to synchronization between the cores and problems like deadlock between the executing cores. Also as per the Moore's Law, number of cores on as ingle processing element increase exponentially becoming double after every 18 months. In the face of such fast increasing cores the time is not far when there will be 100 or 1000 of cores on a single chip. Then there will be bigger challenges of dealing with problems like heat dissipation, concurrency control and speedy communication between the cores, without compromising the performance and outcome of embedded systems employing these multiple cores. In this paper we have studied some of the pre existing protocols and technologies for handling concurrency in large number of multi core systems and have proposed a framework for concurrency control with a routing protocol for multi core system employing 64 cores. Then we have proposed to scale this system for higher number of cores leading to up to 100 cores and w ill study the performance on an embedded system.

Heterogeneous platforms integrating several CPU cores and GPU accelerators have established in several application domains, from desktop, server and mobile. To take full advantage of such platforms, video encoders/decoders have to exploit a broader design space, by cooperatively executing in all the available CPU and GPU cores. To attain such objective, three novel contributions that aim the exploitation of the maximum parallelism level in an HEVC deblocking filter are presented: i) a highly optimized CPU parallel implementation, which outperforms the current state of the art; ii) the first known GPU implementation of the HEVC deblocking filter; and iii) an hybrid and load-balanced CPU+GPU implementation, where all the available resources cooperatively execute, in order to maximize the attained performance. The obtained experimental results demonstrated the ability to achieve processing times as low as 0.8 ms and 0.5 ms to filter 1080p I-type and B-type frames, respectively, corresponding to speedup factors as high as 17 and 9.

Computer architecture is now at an important juncture as single-core CPU power is expected to be nearly constant. The microprocessor industry is rapidly moving towards chip multi-processors (CMPs), commonly referred to as multi-core processors. The transition of CPUs from single to multi-core implementations requires a corresponding shift in the programming paradigm for grid and e-science libraries. Naive implementations of processing on multi-core systems can severely impact performance because of limitations of shared bus bandwidth, cache size and coherency, and communication between threads. To optimize the performance of e-science services, careful application of thread-level parallelism is needed. We study this problem in the context of processing XML data used in grid and e-science applications. The web services model, which strongly leverages XML, has been adopted as the basic architecture for grid and e-science services. As a result, the optimization of separate Web services applications is critical because Web services that are deployed in a longer chain of service processing events must guarantee minimal response times to ensure overall system performance. Our goal is to analyze and provide insightful feedback on cache behavior of each core and reveal performance limitations, bottlenecks, and multi-threaded optimization opportunities for processing XML data relevant to grid and e-science application data formats. We use a micro-architectural emulation framework, Multi-core Grid (McGrid), to generate performance data at various levels of granularity. We analyze cache behavior to quantify the exact gains and present recommendations for processing XML data in grid and e-science applications that will be deployed on emerging multi-core systems.

Dynamic Thermal Management techniques have been widely accepted as a thermal solution for their low cost and simplicity. The techniques have been used to manage the heat dissipation and operating temperature to avoid thermal emergencies, but are not aware of application behavior in Chip Multiprocessors (CMPs). In this paper, we propose a temperature-aware scheduler based on applications' thermal behavior groups classified by a K-means clustering method in multicore systems. The application's thermal behavior group has similar thermal pattern as well as thermal parameters.With these thermal behavior groups, we provide thermal balances among cores with negligible performance overhead. We implement and evaluate our schemes in the 4-core (Intel Quad Core Q6600) and 8-core (two Quad Core Intel XEON E5310 processors) systems running several benchmarks. The experimental results show that the temperature-aware scheduler based on thermal behavior grouping reduces the peak temperature by up to 8degC and 5degC in our 4-core system and 8-core system with only 12% and 7.52% performance overhead, respectively, compared to L.inux standard scheduler.

Optimization of Multi-Phase Compressible Lattice Boltzmann Codes on Massively Parallel Multi-Core Systems

Network processors (NPs) typically contain multiple concurrent processing cores. State-of-the-art programming techniques for NPs are invariably low-level, requiring programmers to partition code into concurrent tasks early in the design process. This results in programs that are hard to maintain and hard to port to alternative architectures. This paper presents a new approach in which a high-level program is separated from its partitioning into concurrent tasks. Designers write their programs in a high-level, domain-specific, architecturally-neutral language, but also provide a separate Architecture Mapping Script (AMS). An AMS specifies semantics-preserving transformations that are applied to the program to re-arrange it into a set of tasks appropriate for execution on a particular target architecture. We (i) describe three such transformations: pipeline introduction, pipeline elimination and queue multiplexing; and (ii) specify when each can be safely applied.As a case study we describe an IP packet-forwarder and present an AMS script that partitions it into a form capable of running at 3Gb/s on an Intel IXP2400 Network Processor.KeywordsGlobal VariableConcurrent TaskConcurrent ProgramSource ProgramTarget ArchitectureThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.