Feedback shift registers, 2-adic span, and combiners with memory

Algebraic feedback shift registers (AFSRs) [] are pseudo-random sequence generators that generalize linear feedback shift registers (LFSRs) and feedback with carry shift registers (FCSRs). With a general setting, AFSRs can result in sequences over an arbitrary finite field. It is well known that the sequences generated by LFSRs can be synthesized by either the Berlekamp-Massey algorithm or the extended Euclidean algorithm. There are three approaches to solving the synthesis problem for FCSRs, one based on the Euclidean algorithm [], one based on the theory of approximation lattices [] and Xu’s algorithm which is also used for some AFSRs []. Xu’s algorithm, an analog of the Berlekamp-Massey algorithm, was proposed by Xu and Klapper to solve the AFSR synthesis problem. In this paper we describe an approximation algorithm that solves the AFSR synthesis problem based on low-dimensional lattice basis reduction []. It works for AFSRs over quadratic integer rings \(\mathbb {Z}[\sqrt{D}]\) with quadratic time complexity. Given the first \(2\varphi _\pi (\mathbf {a})+c\) elements of a sequence \(\mathbf {a}\), it finds the smallest AFSR that generates \(\mathbf {a}\), where \(\varphi _\pi (\mathbf {a})\) is the \(\pi \)-adic complexity of \(\mathbf {a}\) and \(c\) is a constant.

Feedback shift registers (FSRs) are used as a fundamental component in electronics and confidential communication. A FSR f is said to be reducible if all the output sequences of another FSR g can also be generated by f and the FSR g costs less memory than f . A FSR is said to be decomposable if it has the same set of output sequences as a cascade connection of two FSRs. Two polynomial‐time computable transformations from Boolean circuits to FSRs are proposed such that the output FSR of the first (resp. second) transformation is irreducible (resp. indecomposable) if and only if the input Boolean circuit is satisfiable. Through the two transformations, it is proved that deciding irreducibility (indecomposability) of FSRs is NP ‐hard. Additionally, FSRs are constructed to show that there exist infinitely many irreducible (resp. indecomposable) FSRs which are decomposable (resp. reducible).

Random number generators represent basic cryptographic primitives. They are widely used in modern security schemes including security protocols, computer security and password sources. In some algorithms (e.g. DSA) or protocols (e.g. zero-knowledge), random numbers are intrinsic to the computation [3]. In all these applications, strength of security depends greatly on the quality of randomness of the source. Pseudo random number generators (PRNGs) play an important role in cryptographic applications, as the security of these systems depends on the assumption that future values in the random sequence can be unpredictable. A linear feedback shift register (LFSR), in effect, implements a binary polynomial generator. These generators find common use for PRNGs. However, the random sequence generated by LFSR can not guarantee the unpredictability in secure system. We have used genetic algorithm to improve LFSR and proposed a novel random number generator with complex architecture and longer period.

Recently, a new class of feedback shift registers (FCSRs) was introduced, based on algebra over the 2-adic numbers. The sequences generated by these registers have many algebraic properties similar to those generated by linear feedback shift registers. However, it appears to be significantly more difficult to find maximal period FCSR sequences. In this paper we exhibit a technique for easily finding FCSRs that generate nearly maximal period sequences. We further show that these sequence have excellent distributional properties. They are balanced, and nearly have the deBruijn property for distributions of subsequences.

Linear feedback shift registers (LFSRs) are essential components of communications systems such as pseudo random bit sequence (PRBS) generators, convolutional encoders, scramblers and randomizers [1, 2]. Fig.1 (left) shows a LFSR scheme in which the XOR gate is operated among two tapped bits i and i+k within the shift register. The result bit is fed to the shift register at the last position (n) and the sequence in the register is 1-bit shifted as well. The experimental setup for demonstrating an all-optical LFSR is shown in Fig.1 (middle). The main components of the scheme are an optical buffer [3], a bit selecting circuit, and a XOR gate. The data vector (A) is generated by modulating the continuous wave (CW) λ s with a 10Gbps non-return-to-zero (NRZ) electrical pattern whose period is T P =33.3168µs. Only 5 bits are used as the initial sequence for the shift register. The travelling time of the packet in the buffer is T L =1.85 µs, meaning that up to 18 round trips can be accommodated by the pattern's period T P but one of those should be preserved for erasing the buffer before it is fetched a new sequence. The initial sequence enters the buffer as well as propagates directly to the bit selecting circuit. Every round trip, a new sequence as a replica of the previous one plus the feedback bit comes out. At the last round trip, a pump signal inserted into the buffer through the circulator will strongly reduce the gain of the semiconductor optical amplifier (SOA). Both the circulating packet and the accumulating in-band amplified spontaneous emission (ASE) noise will be suppressed. The buffer is now completely cleaned for a new cycle. The first and the last bits of the 1-bit shifted sequence are selected for the XOR operation. Referring to Fig.1 (left), i=1 and k=4, n=5. With this setup, the bit selecting circuit requires 2 clock signals (C) for tap the proper bits from the incoming sequence. The sampling process is done by exploiting four-wave-mixing (FWM) in a 250m-long highly nonlinear fiber (HNLF). Since at every round trip the sequence must be 1-bit shifted, the sampling clocks must be accordingly delayed for 1 bit, resulting the clock period of T C =T L +T B where T B =100ps is the bit time. The outputs of the bit selecting circuit are fed as pump signals to port a and d of a SOA Mach Zehnder interferometer (MZI). They are synchronized with a clock at λ s used as the probe signal (F) at port b. The output of the XOR gate is then fed back into the buffer. The feedback bit should be precisely allocated at the end of the packet circulating inside the buffer, meaning that the feedback time should be T F =T L +T B +T seq in which T seq is the original sequence duration and equal to 500ps in our setup. Fig.1 (right) depicts the results at the 10th round trip for two different input initial sequences (10001) and (10011) taken at point (B). The equalization between bits in the sequence and the quality of the pulses is strongly limited by the accumulating ASE noise inside the buffer, the long fiber-based structure and the bit's polarization. The fiber-based setup also causes misalignment between the clocks, spoils the essential synchronism and degrades the performance of the FWM and the XOR operation. One possible solution for solving all of these problems and hence improving the performance is the integration approach. The bit selection could be implemented exploiting nonlinear effects into an SOA or a periodic-poled lithium niobate (PPLN) instead of using a long HLNF. Moreover the extinction ratio of the pulses at the SOA-MZI XOR output (<13.5dB) could be improved, e.g. with a saturable absorber at its output, thus increasing the number of allowed round trips into the shift register and reducing the noise on the final bit sequence.

This paper starts with stream ciphers based on linear feedback shift registers. A scheme is proposed where both the public key cryptography and the concept of linear feedback shift registers are used. The plaintext message is encrypted with n-Linear Feedback Shift Registers (LFSRs) and secret key, i.e, Initialization vector (IV) of LFSR is being sent with the help of latest public key cryptographic technique, RSA Algorithm. The suggested scheme is successfully applied on text files and on HTML files. The resultant time complexities for different file sizes are shown in tabular format and explained graphically

A low-overhead scheme for achieving complete (100%) fault coverage during built-in self test of circuits with scan is presented. It does not require modifying the function logic and does not degrade system performance (beyond using scan). Deterministic test cubes that detect the random-pattern-resistant (r.p.r.) faults are embedded in a pseudorandom sequence of bits generated by a linear feedback shift register (LFSR). This is accomplished by altering the pseudorandom sequence by adding logic at the LFSR's serial output to fix certain bits. A procedure for synthesizing the bit-fixing logic for embedding the test cubes is described. Experimental results indicate that complete fault coverage can be obtained with low hardware overhead. Further reduction in overhead is possible by using a special correlating automatic test pattern generation procedure that is described for finding test cubes for the r.p.r. faults in a way that maximizes bitwise correlation.

Pseudonoise sequences generated by linear feedback shift registers [1] with some nonlinear combining function have been proposed [2]–[5] for cryptographic applications as running key generators in stream ciphers. In this correspondence it will be shown that the number of trials to break these ciphers can be significantly reduced by using correlation methods. By comparison of computer simulations and theoretical results based on a statistical model, the validity of this analysis is demonstrated. Rubin [6] has shown that it is computationally feasible to solve a cipher proposed by Pless [2] in a known plaintext attack, using as few as 15 characters. Here, the number of ciphertext symbols is determined to perform a ciphertext-only attack on the Pless cipher using the correlation attack. Our conclusion from the analysis is that the pseudonoise generator's output sequence and the sequences generated by the linear feedback shift registers should be uncorrelated. This leads to constraints for the nonlinear combining function to be used.

In order to scale down a circuit size for hardware realization of neural network systems, there are many researches on a conventional pulse model neuron, in which, a conventional numerical calculation is replaced by a stochastic calculation. In the conventional stochastic calculation, LFSR (linear feedback shift register) has been used as a random number generator. In general, a good randomness is required for an exact calculation result. However, since the random numbers which are generated by LFSR is lacking in the randomness, there is a problem which affects an accuracy of the conventional stochastic calculation which uses LFSR for generating the random numbers. In our work, in order to improve the accuracy of the conventional stochastic calculation, we propose to use GLFSR (generalized-LFSR) which generates the random numbers which are rich in randomness as the random number generator for the stochastic calculation. The accuracy of the stochastic calculation is also evaluated using a standard deviation value (SD) and a maximum error. As a result, the proposed stochastic calculation which using GLFSR as the random number generator shows a highest accuracy of the calculation result.

This paper presents a new proposal to generate optimal pseudorandom numbers with Gaussian distribution. The generator is especially designed for low-cost hardware implementation, although the software version is also considered. For this reason, Linear Feedback Shift Registers in conjunction with cyclic rotations are employed. The proposal presents a low implementation cost and overcomes the limitations of the previous Gaussian generators based on linear feedback shift registers by means of a less complex algorithm to find optimal configurations. As a consequence, it turns into a really usable generator. Moreover, a further improvement, based on the simulated annealing algorithm, is applied in order for the random values to be better adjusted to the normal distribution.

Communication security that depends on chaos can be considered as a new approach which provides protection and security of communications and maintains confidentiality because Chaos theory can be implemented in cryptosystem successfully. A stream cipher, on the other hand, is a type of symmetric cryptosystem in which the plaintext is divided into small entities known as characters. The key in stream cipher is typically generated by a random bit generator. Many key stream generators employ linear feedback shift registers (LFSRs). LFSR systems are made up of a group of LFSR units and a combining function (CF) unit. The plaintext is encrypted one bit at a time. The key is fed into a random bit generator, which produces a long series of binary signals. This "key-stream" k is then combined with plaintext m, typically via a bit-wise XOR (Exclusive-OR modulo 2 addition), to produce the ciphertext stream, which employs the same random bit generator and seed. In this paper we will introduce a new stream cipher keygenerator which using a hybrid between chaotic and combination of Linear Feedback Shift Registers (LFSR's). The proposed generator can be used to protect different types of data files (text, image, audio and video). Many kinds of tests are applied to specifying the goodness of the proposed keygenerator. The results of testing prove the efficiency of the suggested system.

In this paper, a 4-bit Linear Feedback Shift Register (LFSR) is implemented based on a well-designed architecture combining using Pass-Transistor (PT) and Clock Complementary Metal Oxide Semiconductor (C2MOS) logic techniques. The D-flip flop registers and the XOR gates are the main parts of the propose LFSR. Number of transistors along with the speed of LFSR were positively enhanced since the exploited logic design techniques tends to blend the flavor of NMOS and PMOS devices. The PSpice and Field Programmable Gate Array (FPGA) based on Hardware Description Language (HDL) are the two different LFSR implementation environments. It has been observed that LFSR performance was effectively improved in terms of size and speed. Therefore, paper’s main aim refers to decreasing in number of transistors as well as speeding up LFSR circuit. A minimum clock time of 5ns was recorded under clearly correct LFSR output patterns. The LFSR circuit Based CMOS techniques can reduce the exploited transistors up to 43% of the conventional C2MOS logic. Besides, the number of transistors being reduced reflects the achieved circuit’s size reduction. It was concluded that paying attention to the design of the main LFSR circuit parts contributes mainly in the enhancement of the whole circuit performance.

To obtain satisfactory fault coverage for testing a logic circuit, linear feedback shift registers (LFSRs) have been used to generate not only the pseudorandom, but also the deterministic patterns in the scan-based built-in self-test environment. However, like other scan-based methods, the LFSR based pattern generation schemes take a long test application time to feed deterministic patterns from the LFSR into a scan chain. In this paper we derive a general relationship between the bits in the scan chain and the states of the LFSR and show that any bit to be generated by an LFSR in any future clock cycle can be pre-generated by a linear function of the current LFSR state. With this relationship, we can divide a scan chain into multiple sub-chains and use one LFSR-based multiple sequence generator to simultaneously generate all the subsequences required by the sub-chains, hence can greatly reduce the test application time for deterministic patterns. Moreover, due to the scan time reduction, test power wasted during the scan operation can also be significantly reduced.

Many Built-in Self Test (BIST) pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs of patterns for delay faults testing with LFSRs. A new synthesis procedure for a n-size LFSR is given and guarantees that a deterministic set of n precomputed test pairs is embedded in the maximal length pseudo-random test sequence of the LFSR. Sufficient and necessary conditions for the synthesis of this pseudo-deterministic LFSR are provided and show that at-speed delay faults testing becomes a reality without any additional cost for the LFSR. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other technique proposed so far.

Random number generator (RNG) is a fundamental element in modern cryptography. If the quality of the outputs generated by RNGs is not as well as expected, the cryptographic applications which use the random number service are vulnerable to security threats. In reality, the entropy source of RNGs could be impressible by the changes of environmental factors, resulting in defects in the generated data, such as poor statistical properties. Thus, RNG is generally designed with a preset post-processing module to improve the quality of the output sequences. Linear feedback shift register (LFSR) is one of the frequently used methods for post-processing thanks to the characteristic of simplicity and no reduction in output throughput. However, we point out that even if the statistical properties of the outputs of the entropy source are extremely poor, the sequences processed by LFSR can still pass the statistical test. This undoubtedly increases the security risks in the usage of RNGs. In this work, we propose a distinguisher for the RNGs with LFSR post-processing for the first time. The distinguisher can be used to detect the RNGs with LFSR post processing, and we theoretically prove the sequences before processing can be recovered. On this basis, we design a new statistical test via combining the distinguisher with the Frequency Test in the NIST test suite. The experimental results show that if the sequence is biased before being processed by LFSR, our proposed method can detect it, but the NIST SP 800-22 Test Suite cannot.KeywordsRandom number generatorLFSRPost-processingDistinguisherRandomness test