Formal Modeling and Analysis of Timed Systems

To cope with large data sets, distributed data stores partition their data across servers. However, real-world systems usually do not provide useful transactional semantics for operations accessing multiple partitions due to the delays involved in achieving multi-partition consistency. Read Atomic Multi-Partition (RAMP) transactions have recently been proposed as efficient light-weight multi-partition transactions that guarantee read atomicity: either all updates or no updates of a transaction are visible to other transactions. In this paper we formalize RAMP transactions in rewriting logic and perform model checking verification of key properties using the Maude tool. In particular, we develop detailed formal models---and formally analyze---a number of extensions and optimizations of RAMP that are only briefly mentioned by the RAMP developers.

This volume contains the proceedings of the 4th International Conference on Formal Modelling and Analysis of Timed Systems (FORMATS 2006), held in Paris (France) on September 25-27, 2006. The aim of FORMATS is to promote the study of fundamental and practical aspects of timed systems, and to bring together researchers from different disciplines that share interests in modelling and analysis of timed systems.

Objective of this contribution is to present the use of Model-based Systems Engineering within the engineering design community. Based on a differentiation between SE and MBSE, the definition of three core MBSE elements, namely modelling method, modelling language, and modelling tool as well as the three major aspects of a consistent system model (requirements, behaviour, and structure) a structured review is conducted, focussing on the understanding and motivation as well as the modelling of systems. The review includes 93 publications from Design Society library and proceedings of the CIRP Design conferences during the period from 2011 to 2022. The review points out, that there is an increasing application of MBSE within the engineering design community, mainly focussing on architecture definition or combined engineering activities. Only a small portion of works (16 publications) are providing a consistent approach as these publications link all aspects of the system model and consider all three MBSE elements. It can be concluded, that there is a diffuse understanding of MBSE and different motivations are given to apply more formal system models as well as modelling tools.

This study deals with the formal modeling and verification of reconfigurable discrete event control systems (RDECSs). The behavior of an RDECS is represented by that of control components (CCs) and the communication among them. A new formalism, called Reconfigurable Timed Net Condition/Event Systems (TNCES) (R-TNCES), is proposed for the optimal functional and temporal specification of RDECS, which is defined by a behavior module and a control module. The former is a union of various superposed TNCESs, where TNCES-based CC modules are basic units. The latter is a set of reconfiguration functions dealing with the automatic transformations of these TNCESs in response to errors or user requirements by enabling or disabling CC modules, changing condition signals and/or event signals among them, and also treating the state feasibility before and after reconfigurations. To control the verification complexity of R-TNCES, a layer-by-layer verification method is developed, where the similarities of different TNCESs in the behavior module are considered. The contribution of this original paper is applied to a benchmark production system.

Context awareness is a computing paradigm that makes applications responsive and adaptive with their environment. Formal modeling and verification of context-aware systems are challenging issues in the development as they are complex and uncertain. In this paper, we propose an approach to use a formal method Event-B to model and verify such systems. First, we specify a context aware system’s components such as context data entities, context rules, context relations by Event-B notions. In the next step, we use the Rodin platform to verify the system’s desired properties such as context constraint preservation. It aims to benefit from natural representation of context awareness concepts in Event-B and proof obligations generated by refinement mechanism to ensure the correctness of systems. We illustrate the use of our approach on a scenario of an Adaptive Cruise Control system.

FORMAL FAILURE MODELS

Formal Modeling and Analysis of Timed Systems

Development processes in various engineering disciplines are incorporating formal models to ensure safety properties of critical systems. The use of these formal models requires to reason about their adequacy, i.e., to validate that a model mirrors the structure of the system sufficiently that properties established for the model indeed carry over to the real system. Model validation itself is non-formal, as adequacy is not a formal (i.e., mathematical) property. Instead it must be carried out by the modeler to justify the modeling to the certification agency or other stakeholders. In this paper we argue that model validation can be seen as a special form of requirements engineering, and that interactive visualization and concepts from requirements traceability can help to advance tool support for formal modeling by lowering the cognitive burden needed for validation. We present the VisualisierbaR tool, which supports the formal modeling of railway operations and describe how it uses interactive visualization and requirements traceability concepts to validate a formal model.

This paper describes the application of Real-Time Maude to the formal modeling, simulation, and model checking analysis of the NORM multicast protocol standard being developed by the Internet Engineering Task Force. Because of its size and sophistication, real-time features, and the need to model and analyze subcomponents of NORM both in isolation and in combination, NORM poses a set of challenging problems for its formal specification and analysis. Our formal modeling and analysis efforts made us aware of ambiguities, inconsistencies, and cases of under-specification in the informal specification of NORM. Our work indicates that formal methods can successfully be applied by non-experts during the development of advanced Internet protocol standards.

The paper examined the problem of modeling and design of software computer systems. The article briefly describes the content aspects of the various stages of the implementation of software complexes and systems. The methodology of research and analysis of systems, which uses the method of computer simulation modeling, is given. The aim of the work is to create a new universal approach to the design and implementation of software systems of various levels of complexity. During the study, the following general scientific methods were used: system analysis, synthesis, formalization, modeling, decomposition, structuring, description, comparison. The materials used in the study were: computers and software development tools. As a result of the study proposed a universal agent-module approach to the design and implementation of software systems based on simulation agent-based modeling. The study presents the processes of modeling and designing software systems, their stages, and the possibility of their integration within the described approach. Examples of formal model and structure of the software system under design based on the agent-module approach are presented. The proposed approach can be used in the process of software development at the initial stages related to modeling and designing of software systems. Integration of modeling and design stages in the proposed approach will significantly reduce software development time and simplify the design process by making it clearer and more formalized. Materials of the article are of scientific and practical value for a wide range of specialists interested in system analysis, modeling, design and implementation of software systems.

A model checker is an automatic tool that traverses a specific structure (normally a Kripke structure referred as the modelM) to check the satisfaction of some (temporal) logical propertyf. This is formally stated asM⊧f. For some formal notations, the modelMof a specificationS(written in a formal languageL) can be described as a labelled transition system (LTS). Specifically, it is not clear in general how usual tools such as SPIN, FDR, PAT, etc., create the LTS representation from a given process. Although one expects the coherence of the LTS generation with the semantics ofL, it is completely hidden inside the model checker itself. In this paper we show how to create a model checker forL, using a development approach based on its operational semantics. We use a systematic semantics embedding and the formal modeling using logic programming and analysis (FORMULA) framework to this end. We illustrate our strategy considering the formal language COMPASS modelling language (CML)—a new language that was based on CSP, VDM and the refinement calculus proposed for modelling and analysis of systems of systems. As FORMULA is based on satisfiability modulo theories solving, our model checker can handle communications and predicates involving data with infinite domains by building and manipulating a symbolic LTS. This goes beyond the capabilities of traditional CSP model checkers such as FDR and PAT. Moreover, we show how to reduce time and space complexities by simple semantic modifications in the embedding. This allows a more semantics-preserving tuning. Finally, we show a real implementation of our model checker in an integrated development platform for CML and its practical use on an industrial case study.

Formal Techniques, Modelling and Analysis of Timed and Fault-Tolerant Systems

The ForSyDe methodology has been developed for system level design. In this paper we present formal transformation methods for the refinement of an abstract and formal system model into an implementation model. The methodology defines two classes of design transformations: (1) semantic-preserving transformations and (2) design decisions. In particular we present and illustrate communication and clock domain refinement by way of a digital equalizer system.

We present a novel notion of deadlock for synchronization on arbitrary boolean conditions and a sound, fully automatic deadlock analysis. Contrary to other approaches, our analysis aims to detect deadlocks caused by faulty system design, rather than implementation bugs. We analyze synchronization on boolean conditions on the fields of an object instead of targeting specific synchronization primitives. As usual, a deadlock is a circular dependency between multiple tasks. A task depends on a second task if the execution of this second task has a side-effect that makes the blocking guard-condition of the first one evaluate to true. This requires an analysis of the computations in a method beyond syntactic properties and we integrate a logical validity calculus to do so.

Aerospace systems have strict dependability and real-time requirements, as well as a need for flexible resource reallocation and reduced size, weight and power consumption. To cope with these issues, while still maintaining safety and fault containment properties, temporal and spatial partitioning (TSP) principles are employed. In a TSP system, the various onboard functions (avionics, payload) are integrated in a shared computing platform, however being logically separated into partitions. Robust temporal and spatial partitioning means that partitions do not mutually interfere in terms of fulfilment of real-time and addressing space encapsulation requirements. This chapter describes in detail the foundations of an architecture for robust TSP aiming a new generation of spaceborne systems, including advanced dependability and timeliness adaptation control mechanisms. A formal system model which allows verification of integrator-defined system parameters is defined, and a prototype implementation demonstrating the current state of the art is presented.