Formal Verification with ABV : A Superior Alternative to UVM for Complex Computing Chips

Functional simulation verification is an important part for Field Programmable Gate Array (FPGA) product verification. Many problems had been encountered in FPGA verification in nuclear instrument control system when adopting traditional verification methods, such as long verification cycle, poor reusability of verification testbench, low level of automation, etc. Universal Verification Methodology (UVM) has the characteristics of reusability, extensibility and automatic. We introduced UVM for FPGA verification, which improved the efficiency and quality of verification process, and saved the project time. At present, this technology had been applied in the IO product verification of Diverse Actuation System (DAS) and achieved good results, and this approach will be applied gradually in the project.

Multicore microarchitecture designs have become ubiquitous in today's computing environment enabling multiple processes to execute simultaneously on a single chip. With these new parallel processing capabilities comes a need to better understand how co-running applications impact and interfere with each other. The ability to characterize and better understand cross-core performance interference can prove critical for a number of application domains, such as performance debugging, compiler optimization, and application co-scheduling to name a few. We proposed a novel methodology for the characterization and profiling of cross-core interference on current multicore systems, which we call contention synthesis. Our profiling approach characterizes an applications cross-core interference sensitivity by manufacturing contention with the application and observing the impact of this synthesized contention on the application.Understanding how to synthesize contention on current chip microarchitectures is unclear as there are a number of potentially contentious data access behaviors. This is further complicated by the fact that current chip microprocessors are engineered and tuned to circumvent the contentious nature of certain data access behaviors. In this work we explore and evaluate five designs for a contention synthesis mechanism. We also investigate how these five contention synthesis engines impact the performance of 19 of the SPEC2006 benchmarks on two state of the art chip multiprocessors, namely Intel's Core i7 and AMD's Phenom X4 architectures. Finally we demonstrate how contention synthesis can be used to accurately characterize an application's cross-core interference sensitivity.

In the competitive CPU market, emphasis is placed on automations that promotes innovation and supports design of multiple CPU configuration which meets schedule and timely turnaround to market. Design automation is essential in the design of different areas of CPU including the global clock distributions. This paper talks about design automation tools developed to handle the design of the global clock distributions for various Intel microprocessors.

Debugging, on average, has grown to consume more than 60% of today's ASIC and SoC verification effort. Clearly, this is a topic the industry must address, and some organizations have done just that. Those that have adopted an assertion-based verification (ABV) methodology have seen significant reduction in simulation debugging time (as much as 50% [1]) due to improved observability. Furthermore, organizations that have embraced an ABV methodology are able to take advantage of more advanced verification techniques, such as formal verification, thus improving their overall verification quality and results. Nonetheless, even with multiple published industry case studies from various early adopters--each touting the benefits of applying ABV--the industry as a whole has resisted adopting assertion-based techniques. This tutorial provides an industry survey of today's ABV landscape, ranging from myths to realities. Emerging challenges and possible research opportunities are discussed. The following extended abstract provides a reference on which the tutorial builds.

This paper shows that electromagnetic (EM) information leakage from modern laptops and desktops (with no peripherals attached) is indeed possible and is relatively easy to achieve. The experiments are performed on three laptop systems and one desktop system with different processors (Intel Centrino, Core 2, Core i7, and AMD Turion), and show that both active (program deliberately tries to cause emanations at a particular frequency) and passive (emanations at different frequencies happen as a result of system activity) EM side-channel attacks are possible on all the systems we tested. Furthermore, this paper shows that EM information leakage can reliably be received at distances that vary from tens of centimeters to several meters including the signals that have propagated through cubicle or structural walls. Finally, this paper shows how activity levels and data values used in accessing different parts of the memory subsystem (off-chip memory and each level of on-chip caches) affect the transmission distance.

Over the past few years the complexity of Multi-Processor System on Chip (MPSoC) designs increased drastically. This made product verification very challenging and illusive. In order to cope with design complexity, Universal Verification Methodology (UVM) associated with System Verilog Assertions (SVA) are used extensively to build up robust verification environments revealing design issues. This work introduces a new methodology verifying SoC design blocks in two modes: Stubbing mode, where all blocks serving the Design Under Test (DUT) are implemented as UVM active and passive agents; Physical hardware mode, where all blocks are physically running along with the firmware driver. A complete SoC system contains: processor, controller, and encryption engine is studied while implementing the proposed verification approach. Functionality check and coverage collection are performed through UVM scoreboard and subscriber respectively. The proposed approach provides the capability of verifying both hardware and firmware simultaneously in the simulation phase.

Summary form only given. Assertion based validation of hardware and software systems has been in use in the industry for a long time. In the software languages such as C++ or Java, there are special assert constructs that are used to specify a Boolean condition. These conditions express what the programmers think ought to hold, at specific points in their programs. Violations of such assertions provide clues about the program state at those points during execution and hence indicate the existence of bugs. In hardware design especially at the RTL and higher abstraction levels, similar assertions have been used originally in proprietary languages, and more recently with PSL (Property Specification Language). PSL was standardized initially by Accellera, and later by IEEE. PSL and similar assertion languages allow not only Boolean expressions, but more complex constructs involving temporal behaviors. Therefore, these languages can be used for checking assertions at certain points of the model execution, as well as for formal property verification. Standardization of PSL gave rise to a lot of interest in the hardware design industry, and various formal and simulation based techniques have been integrated into the validation tools from the various EDA companies. The question in front of the panel is if the assertion based verification a panacea for the validation gap problem in the design industry, and if not, where the short comings are. Industry experts from Synopsys, Cadence, Mentor Graphics, Real Intent, and from Academia debated these questions at this panel

The serial peripheral interface (SPI) is an important module for realizing communication between the APB bus in the SOC chip and peripheral SPI devices. Therefore, efficient and sufficient verification of the function of the SPI module is very important for the design and manufacture of the SOC chip. In this article, a verification environment for SPI module is built based on universal verification methodology (UVM). By introducing the register abstraction layer (RAL), the efficiency of register attribute checking and configuration is greatly improved. In addition, the use of constrained random excitation and automatic result comparison function has realized the full verification of the SPI function, with a coverage rate of 100%. Finally, the verification environment of the SPI module has been successfully migrated to the SOC verification environment.

Today’s scenario of semiconductor technology is a tremendous innovation; it includes a large number of intellectual property (IP) cores, interconnects, or buses in system on chip (SOC) design and based upon the necessity its complexity keeps on increasing. Hence, for the communication between these IP cores, a standard protocol is developed. The necessity of IP reuse, abridging the design time and the complexity makes large-scale SOC more challenging in order to endorse IP core reusability for SOC designs. An efficient non-proprietary protocol for communication between IP cores is open core protocol (OCP). OCP comes under socket-based interface and openly licensed core concentric protocol. This paper addresses on the verification of implemented design of OCP. The proposed paper is to verify the implemented design by using System Verilog and Universal Verification Methodology (UVM) in SimVision tool.

The Accellera EDA standards body has recently approved the PSL a standard property specification language for use in assertion-based verification via simulation and formal verification tools. This language, which is based on the Sugar language from IBM, is now supported by many EDA vendors. More than 40 individuals representing over 20 companies participated in the efforts to form the PSL standard from its Sugar basis.The tutorial comprises 2 parts. In the first part, we describe the basic principles of PSL/Sugar, focusing on the ease with which complex design behaviors may be described with concise, readable PSL/Sugar assertions that crisply capture design intent. We summarize the temporal constructs of the language, including parameterized sequences and properties, directives, and modeling capabilities. We cover the general timing model of PSL/Sugar, which transparently supports both (single- or multi-clock) synchronous and asynchronous design, and, time permitting, we explain how PSL/Sugar has been defined to ensure consistent semantics for both simulation and formal verification applications.In the second part of the tutorial, we present several applications of PSL/Sugar, ranging from simple to advanced assertion-based verification solutions. These include use of PSL/Sugar for dynamic assertion checking and formal model checking, including support for environment modeling and assume/guarantee reasoning. Examples of commercial verification tools which support the PSL/Sugar languages will also be presented.Participants in the tutorial will have an excellent opportunity to learn about both the language and its applications directly from the speaker, Dr. Danny Geist, who heads a research group in the IBM Haifa lab where Sugar was conceived.

The objective of the project is to develop the I2C Master RTL using VHDL and verify it using UVM. I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices, suitable for short-distance communication between multiple devices. The I2C Master facilitates communication between the Core and various slaves in the chip. The I2C Master IP implemented here is a subset of the full I2C protocol, as some features are not supported. The RTL design of I2C is open source, and its functional verification is performed using System Verilog and UVM. The Universal Verification Methodology was developed to provide a well-structured and reusable verification environment without interfering with the device under test (DUT). This paper highlights the reusability of I2C using UVM, details the construction of the verification environment, and describes the implementation of test cases for this protocol. Additionally, the performance metrics and verification coverage results are discussed, demonstrating the efficiency and robustness of the developed environment. The results show significant improvements in verification time and accuracy, validating the approach.

The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger latency buffering section of pixel chips. A fully shared architecture and a distributed one have been described at behavioral level and simulated; the resulting memory occupancy statistics and hit loss rates have subsequently been compared.

System on Chip (SoC) designs inherit all the well known verification and validation difficulties associated with complex ASIC designs, besides adding their own set of newer problems. These arise because SoCs are primarily implemented by re-using Intellectual Property (IP) cores. It is well known that verification today constitutes about 70% to 80% of the total design effort, thereby, making it the most expensive component in terms of cost and time, in the entire design flow. It is expected to get even worse for SoC designs. In a complex SoC design flow functional verification is very important; any behavioral or functional bug escaping this phase will not be detected in the subsequent implementation phases and will surface only after the first silicon is integrated into the target system, resulting in costly design and silicon iterations. A number of academic and industrial research laboratories have been carrying out research on functional verification of SoCs based on different approaches. Partial success has been achieved in deploying them. Many of the issues relate to intrinsic limitations of some of the approaches taken; while others have to do with the quality of the design information, by way of, design descriptions, design documentations and design specifications, from which the overall verification objectives are derived. SoCs have brought to focus the need to carry out design and verification concurrently. For the design and verification task to proceed concurrently there is a need to capture formally, design information and implementation details at various levels of abstraction. Another reason for the need to formalize is that, as designs become more complex, functional verification will have to be carried out using the divide and conquer approach.We discuss several approaches based on compositional verification. For these approaches to succeed, specifications of either, the individual modules, or individual IPs, if any are used, have to be stated formally. There exist several commercial offerings addressing the area of SoC functional verification. Most of these use some form of divide and conquer approach related to compositional verification. The basis of success of some of these tools lies in the fact that the specifications of the IP cores are in essence captured in some executable form, be they formal specification languages, or commonly used HDLs suitably modified for the purpose.This tutorial is structured to provide information on the state of the art in the area of functional verification. It will focus on existing methodologies, tools, and practical approaches based on universal simulation, emulation, formal verification, and semi-formal verification that can be employed to overcome the SoC verification problem. We discuss a number of real life verification projects, describing the various techniques used and the effectiveness of these techniques. We conclude the tutorial by presenting issues, which form the current focus for research.

The design of Renewable Energy Power Plants (REPPs) is crucial not only for the investments' performance and attractiveness measures, but also for the maximization of resource (source) usage (e.g. sun, water, and wind) and the minimization of raw materials (e.g. aluminum: Al, cadmium: Cd, iron: Fe, silicon: Si, and tellurium: Te) consumption. Hence, several appropriate and satisfactory Multi-Objective Problems (MOPs) are mandatory during the REPPs' design phases. MOPs related tasks can only be managed by very well organized knowledge acquisition on all REPPs' design equations and models. The proposed MOPs need to be solved with one or more multi-objective algorithm, such as Multi-Objective Evolutionary Algorithms (MOEAs). In this respect, the first aim of this research study is to start gathering knowledge on the REPPs' MOPs. The second aim of this study is to gather detailed information about all MOEAs and available free software tools for their development. The main contribution of this research is the initialization of a proposed multi-objective evolutionary algorithm knowledge acquisition system for renewable energy power plants (MOEAs-KAS-F-REPPs) (research and development loopwise process: develop, train, validate, improve, test, improve, operate, and improve). As a simple representative example of this knowledge acquisition system research with two selective and elective proposed standard objectives (as test objectives) and eight selective and elective proposed standard constraints (as test constraints) are generated and applied as a standardized MOP for a virtual small hydropower plant design and investment. The maximization of energy generation (MWh) and the minimization of initial investment cost (million €) are achieved by the Multi-Objective Genetic Algorithm (MOGA), the Niched Sharing Genetic Algorithm/Non-dominated Sorting Genetic Algorithm (NSGA-I), and the NSGA-II algorithms in the Scilab 6.0.0 as only three standardized MOEAs amongst all proposed standardized MOEAs on two desktop computer configurations (Windows 10 Home 1709 64 bits, Intel i5-7200 CPU @ 2.7 GHz, 8.00 GB RAM with internet connection and Windows 10 Pro, Intel(R) Core(TM) i5 CPU 650 @ 3.20 GHz, 6,00 GB RAM with internet connection). The algorithm run-times (computation time) of the current applications vary between 20.64 and 59.98 seconds.

Thread-Level Speculation (TLS) is a hardware/software technique that enables the execution of multiple loop iterations in parallel, even in the presence of some loop-carried dependences. TLS requires hardware mechanisms to support conflict detection, speculative storage, in-order commit of transactions, and transaction roll-back. There is no off-the-shelf processor that provides direct support for TLS. Speculative execution is supported, however, in the form of Hardware Transactional Memory (HTM)—available in recent processors such as the Intel Core and the IBM POWER8. Earlier work has demonstrated that, in the absence of specific TLS support in commodity processors, HTM support can be used to implement TLS. This paper presents a careful evaluation of the implementation of TLS on the HTM extensions available in such machines. This evaluation provides evidence to support several important claims about the performance of TLS over HTM in the Intel Core and the IBM POWER8 architectures. Experimental results reveal that by implementing TLS on top of HTM, speed-ups of up to 3.8\(\times \) can be obtained for some loops.