Freqency Compensation for Multistage Amplifiers using Active-Feedback Current Buffers

This brief presents a single-capacitor active-feedback compensation (SCAFC) scheme for three-stage internal amplifiers driving small capacitive loads. The proposed SCAFC scheme can stabilize the three-stage amplifier by using only a single small-value compensation capacitor, thereby significantly reducing the amplifier implementation area. With the small-value compensation capacitor, the wide gain-bandwidth product (GBW) of the SCAFC amplifier can also be achieved under low-power conditions. Implemented in a standard 0.35-mum CMOS process, the proposed three-stage SCAFC amplifier achieves over 100-dB dc gain, 9.6-MHz GBW, and 6.1-V/mus average slew rate, by only dissipating 90 muW at 1.5 V and using a 1-pF compensation capacitor, when driving a 500-kOmega // 20-pF load. The proposed SCAFC amplifier experimentally improves both bandwidth-to-power and slew-rate-to-power efficiencies by more than 14 times and 9 times, respectively, as compared to a conventional three-stage nested-Miller-compensated amplifier.

A low impedance receiver for power efficient current mode signalling across on-chip global interconnects

This paper presents a high-gain wide-bandwidth two-stage amplifier. By adopting the recycling folded cascode input-stage, a damping-factor-control frequency compensation (DFC) and a feedforward stage, the designed two-stage amplifier achieves well performance such as the gain-bandwidth product (GWB) and the slew rate (SR). The two-stage amplifier has been designed in a standard 0.5µm CMOS process and is simulated using a 3-V power supply and a 25-kΩ//100-pF load. Simulation results show that the designed two-stage amplifier achieved a DC gain of about 100dB, GWB of 26.6MHz with 60.1° phase margin and SR+/SR−=24.4/13.35-V/µs.

ABSTRACTA structure for a low input impedance current buffer transimpedance amplifier (CBTIA) is presented, which holds great potential for flexible bioelectronic applications requiring high linearity sensing and transmission. Based on this structure, a tunable CBTIA and a low input impedance CBTIA circuits are implemented. The former utilizes a current sink input mode, where the voltage at the drain of common gate transistor is fed back to the gate of input current sink transistor in order to achieve low input impedance. A self‐biasing optimization (SBO) technique is proposed for self‐regulation of voltage headroom at each node. Additionally, the active load constructed by pseudo current source converts the current to voltage. Due to the current sink input mode, this design ensures that adjusting the transimpedance gain does not affect the input impedance. Furthermore, in the second circuit design, feedback is provided to the gate of an SBO regulated transistor in order to achieve even lower input impedance. The proposed CBTIAs were successfully implemented using 10‐ m IZO TFT technology. Test results show that the tunable CBTIA achieves a transimpedance gain range of 15.2 K to 47.4 K while maintaining an unchanged 2 K input impedance, and the low input impedance CBTIA achieves an input impedance less than 1.3 K with a 61.7 K transimpedance.

An optoelectronic circuit integrated with a photodiode is proposed, which simultaneously achieves 3.5-MΩ transimpedance gain and 18-MHz bandwidth. The design is intended to address the limits on bandwidth introduced by the large parasitic capacitance of the integrated photodiodes in optoelectronic applications. The proposed circuit consists of a transimpedance amplifier (TIA) and a voltage gain stage. The pre-stage TIA with low input impedance provides the main transimpedance gain of the circuit over a wide bandwidth. The post voltage gain stage provides the supplemental voltage gain for the circuit and increases its driving capability. The circuit is fabricated in a 0.5-μm CMOS process with an active area of 501.2 μm × 291.6 μm. When the light input is a 100-ns pulse with 905-nm wavelength and 1.5-μW optical power, the amplitude of output signal is 1.6 V with a rise time of 24.5 ns and a delay time of 21 ns.

In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple mirror/source structure with input and output voltage requirements less than that of a simple current mirror is presented. It can be also used as variable negative impedance converter (variable-NIC) by modifying amplifier transistors' aspect ratios. The circuit's principle of operation is discussed and compared to simple and low voltage cascode (LVC) current mirrors. Working with power supplies less than 1volt, the proposed circuit provides output impedance greater than LVC current mirror. Such outstanding features of this current mirror as high output impedance~25.3M, low input impedance~44, wide bandwidth~498 MHz, low input voltage ~ 415 mV, low output voltage ~ 149 mV and low current transfer error ~1.3% (all at 10 ¿A) makes it an outstanding choice for high performance applications. Simulation results in BSIM 0.35 ¿m CMOS technology with Hspice are given in comparison with simple, and LVC current mirrors to verify and validate the performance of the proposed current mirror/NIC.

Implantable bioimpedance monitoring has the potential to be an extremely powerful tool for biomedical research and healthcare. Currently, signal processing, specifically analog-to-digital conversion, does not allow for power-efficient conversion of bioimpedance data over a wide spectrum of frequency. In this paper, a reconfigurable pipelined analog-to-digital converter, for bioimpedance monitoring applications is presented. The converter can operate with a sampling rate between 100 kS/s to 20 MS/s and a resolution of 8 or 10 bits depending on the signal amplitude. Furthermore, the converter is self-configurable in terms of sampling rate and resolution based on the frequency and the amplitude of the input signal. A competitive FOM range (51.7---157 fJ/conv) is achieved by taking advantage of weak-inversion-biased transistors and utilizing an interference elimination technique in the 3rd pipeline stage to increase the power efficiency. The system is realized in a standard 130 nm CMOS process and consumes 16.1 μW and 1.06 mW in 8-bit and 10-bit mode, respectively. The core area of design is only 0.426 mm2. Test results show that the proposed ADC can successfully digitize the voltage drop across a bovine cell impedance model that is derived for an implantable bioimpedance measurement sensor application using the multi-electrode array of vertically aligned carbon nanofibers (VACNF).

This paper proposes a dual-path frequency compensation (DPFC) for implementing on-chip error amplifier (EA). The DPFC uses two operation amplifiers to simultaneously charge and discharge a compensation capacitor. As a result, the equivalent capacitance is significantly multiplied with small additional power and silicon area. Since the slew rate of the EA is increased owing to the small compensation capacitance, the transient response of the buck converter is also enhanced dramatically. A laboratory converter with the DPFC is implemented with 0.35-μm CMOS process. Simulation results demonstrate the converter stability and transient response. The transient recovery time is less than 4 μs for load current changing from 500 mA to 50 mA. With the DPFC, the compensation capacitor is shrunk significantly and no compensation resistor is needed.

An ultra high slew rate recycling folded cascode OTA with 100-dB DC gain

In this paper, a three-stage class AB operational transconductance amplifier (OTA) with large slew rate is presented. The reversed nested Miller compensation technique is used to stabilize the proposed OTA, allowing the slew rate enhancement to be achieved by using class AB input and output stages. A flipped-voltage follower cell in the first stage in combination with a switched-capacitor level shifter in the last stage are utilized to implement the class AB operation. Circuit level simulation results are provided using HSPICE and a 90 nm CMOS technology which show 306 % enhancement in the large-signal FoM with approximately the same power dissipation compared to the class A OTA. The achieved settling time with 0.02 % accuracy for the proposed class AB and conventional class A OTAs are 7.5 and 15.3 ns, respectively.

This paper describes a current mode integrator and filter. The circuit can operate at high cutoff frequency and has low input impedance. The design of current mode integrator is based on a low input impedance current mirror with grounded capacitors. The integrator provides a building block for using in active filter circuits based on the doubly terminated LC ladder filter prototype. A 5th order low pass active ladder filter using the integrator is designed as an example and simulated by H-SPICE using the standard 0.5 μm CMOS technology. The designed cutoff frequency of the filter is 200 MHz and can be electronically tuned from 90−250 MHz by varying the DC bias current. The input impedance of the filter is low (11 ohm). The power dissipation is 1.2 mW/pole and is very practical when operated with a voltage supply of 1.5 V.

Nowadays, current passive mixers represent the state of the art for signal down-conversion in wireless receivers. In such kind of structures, noise, distortions and losses are strictly correlated to the performance of the stage following the mixer. The most common solution adopted to sense the down-converted current is a transimpedance amplifier (TIA) in shunt with a capacitance to ground that assures a low input impedance when the loop gain of the amplifier decreases (Fig. 20.9.1a). A low input impedance is necessary to have a small voltage swing at the output of the mixer (typically few hundreds mV) to minimize the modulation of the switch resistance and with it the distortion produced during the downconversion. The input capacitance can also be used to filter the majority of the out-of-band interferers by transforming the TIA into a filter [1,2] (Fig. 20.9.1b). This reduces the dynamic range required by the TIA and its power consumption. This advantage comes at a cost of area, since the limited voltage swing tolerable at the input of the TIA demands a large capacitor to absorb the downconverted interferers. This trade-off is relaxed with the proposed solution (Fig. 20.9.2), where the input capacitance (C1) is partially boosted by a feedback network minimizing the swing required at the input of the TIA. This idea, originally proposed in [3] only to improve the 1dB compression point, is now used to maximize the spurious-free dynamic range of the TIA, exploiting an intrinsic in-band highpass shaping of noise and distortion. Furthermore, an adaptive transfer function, which improves its filtering action in presence of large out-of-band interferers, is realized.

A new Floating gate metal oxide semiconductor (FGMOS) and a CMOS Resistor-based current mirror (RBCM) with very low voltage requirement at input and output voltage is presented in this paper. The proposed circuit employs two resistors arranged in a symmetrical configuration, one control circuit and FGMOS the resulting error in two resistors circuits is subtracted to each other, this property reduces error and improves precision. The circuit is designed and investigated by using Cadence virtuoso, EDA tool with 180 nm technology under supply voltage of 0.75 V. This circuit has the advantage of high output impedance, low input impedance, wide input swing, large output swing, high linearity which makes this circuit a preferred choice for high performance low-voltage, wide range of input voltage and low-power application. The simulation results show are quite motivating as this circuit offers extremely low input impedance of 370 <tex>$\Omega$</tex>, output impedance of 1 <tex>$7\mathrm{M}\Omega$</tex> and power consumption of 150 <tex>$\mu$</tex> A.

An input-output rail-to-rail buffer amplifier is presented that is low noise, fast, and operates at ultra low currents. The amplifier targets energy harvesting applications that require low cost, high volume, and rugged manufacturing by avoiding use of non-standard device configurations or special processes. The main contributions of this work are: (1) The method of lowering voltage output noise by narrow-banding an amplifier, while introducing a time dependent bias current boost that is triggered by large differential input signals. Narrowbanding an amplifier to reduce its output noise, slows its dynamic response, and this method aims to restore and boost both the amplifier's slew rate and settling time. (2) Amplifier can operate at low VDD of about VGS+2VDS, while running in subthreshold, based in standard 0.18u digital CMOS. (3) PMOSFETs are utilized as inputs, compensation capacitors, and bias resistors in both the amplifier and the boost stages, which helps optimize for yield and lower noise. More importantly, the dynamic response of both the main amplifier and the boost stage being substantially dependent on PMOSFET device parameters, facilitates a smoother dynamic response in and out of boost, over process and operating variations. Based on montecarlo (MC) and worst case (WC) simulations, the following specifications are achievable: voltage output noise (VO nOiSe ) of 10 uv/Hz⁁1/2 at 1KHz, supply current (Idd) ∼ 500 nA; V dd minimum ∼0.6V; rail-to-rail voltage input (V IN ) range and output voltage (V OUT ) range of ∼ +/− 25mv from the rails; output resistor load (R l ) ∼2k Ohms; output capacitor load (C l ) ∼1nF; slew-rate (SR) −/+ ∼ 4/2.5 v/us; settling time (t S ) ∼ 5us to 1%; power supply rejection ratio (PSRR) −/+ ∼ 80dB/85dB, common mode rejection ration (CMRR) ∼ 125dB, unity gain bandwidth (f r ) ∼ 20KHz with phase margin (PM) ∼ 75 degrees; open loop gain (G) ∼ 85dB; preliminary area estimate of ∼ 180 um per side.

When attempting to stabilize a multi-stage amplifier, the introduction of a Miller capacitor may create a feed-forward path and Right-Half-Plane (RHP) zero, jeopardizing the stability of the control loop. In addition to a nulling resistor, a voltage buffer or a current buffer can be placed in series with the Miller capacitor to obviate the feed-forward path and introduce a Left-Half-Plane (LHP) zero. A LHP zero, placed in its proper location, can cancel the effect of a pole and/or an RHP zero, boosting the phase margin, and improving large-signal stability. This tutorial starts with the basics of frequency compensation. We explain some of the complex details in analyzing a wide range of compensation networks for multi-stage amplifiers. We introduce frequency compensation techniques using current buffers. In addition to the popular common-gate (or cascode) transistor topology used as a positive current buffer, we detail the recent technique of using current mirror as an inverting current buffer. Simple design equations and design examples of frequency compensation using current buffers are detailed. The tutorial concludes by introducing an effective method of using a series resistor for accurate placement of current buffer LHP zeros.