Single-Capacitor Active-Feedback Compensation for Small-Capacitive-Load Three-Stage Amplifiers

A frequency compensation scheme based on an active-feedback current buffer (AFCB) is presented in this paper. With an active-feedback mechanism, the proposed AFCB offers quite low input impedance across wide frequency spectrum, which greatly reduces the power consumption of AFCB amplifiers employing the AFCB as frequency compensation. The bandwidth and slew rate of the AFCB amplifier are also improved due to the much smaller compensation capacitors. Moreover, the presence of a left-half-plane zero in the AFCB amplifier enhances the stability and settling behavior of the amplifier. A three-stage AFCB amplifier is implemented by a standard 0.5-mum CMOS process. When driving a 120-pF capacitive load, the AFCB amplifier achieves over 100-dB DC gain, 4-MHz gain-bandwidth product (GBW), 65deg phase margin, and 1.9-V/mus average slew rate with total 3.5-pF compensation capacitances, while only dissipating 160-muW power at a 2.5-Vsupply

This paper presents a very low-voltage low-power pipelined ADC with 0.9-V supply voltage in a 90 nm CMOS process. A novel switched-RC sampling MDAC is proposed to obtain high linearity under very low-voltage and low-power conditions without significant degradation in speed or causing any reliability problem. Moreover, by eliminating S/H stage, power consumption is reduced considerably. Pipelined stage scaling, dynamic comparator, and amplifier sharing are also utilized to reduce power more significantly. According to HSPICE simulation results, the 10-bit 100MSample/s ADC with 1-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p-p,diff</sub> input signal in a 90 nm CMOS process and 0.9-V supply voltage achieves an SNDR of 59 dB and consumes 15.5 mW power.

This paper presents a three-stage low-voltage bulk-driven sub-threshold class AB current mirror load operational transconductance amplifier (OTA) which utilizes FVF based input core and feed-forward compensation techniques for its low-voltage operation to drive high capacitive load. This three-stage OTA provides a gain of 94.4 dB, gain bandwidth (GBW) of 14.2 kHz and phase margin (PM) of 64 degree with load capacitor (Cl) and two small compensation capacitors (Cc1 and Cc2) of 100 pF, 2 pF and 0.02 pF, respectively. This OTA has ensured the total harmonic distortion (THD) of −49 dB for 0.5 Vpp input signal of 200 Hz frequency, while driving 100 pF load in its unity gain configuration. Biased with a single supply of 0.5 V it has consumed quiescent power of 104 nW. It offered high common mode rejection ratio (cMRR) and power supply rejection ratio (PSRR) of 138 dB and 81 dB, respectively at 1 Hz. Simulations results are performed using standard n-tub 180 nm CMOS process with UMc technology file in cadence spectre environment.

This paper designs a wideband low-noise amplifier (LNA) covering wideband of 7-18 GHz. This wideband LNA design adopts the shunt-series peaking technique to improve the high frequency gain response, and three-stage amplifier further extends the bandwidth (BW). The unique properties of ladder filter are used to match an inductively degenerated transistor to a 50 $\Omega$source over a wide band. Based on the 0.13-$\mu$m CMOS process, the simulation results show that the wideband LNA achieves a gain flatness of 22 ± 0.5 dB in the range of 7-18 GHz, the return loss (S$_{\mathbf{11}}$) is less than −9.6 dB, the whole circuit noise Figure (NF) is 2.29-2.7 dB.

This paper proposes a dual-path frequency compensation (DPFC) for implementing on-chip error amplifier (EA). The DPFC uses two operation amplifiers to simultaneously charge and discharge a compensation capacitor. As a result, the equivalent capacitance is significantly multiplied with small additional power and silicon area. Since the slew rate of the EA is increased owing to the small compensation capacitance, the transient response of the buck converter is also enhanced dramatically. A laboratory converter with the DPFC is implemented with 0.35-μm CMOS process. Simulation results demonstrate the converter stability and transient response. The transient recovery time is less than 4 μs for load current changing from 500 mA to 50 mA. With the DPFC, the compensation capacitor is shrunk significantly and no compensation resistor is needed.

An output-capacitor-free multi-stage low-dropout regulator (LDO) with new compensation scheme is presented. This scheme relieves the requirement of compensation capacitor to be 1.2 pF by making use of the large gate capacitance of pass transistor as a large on-chip compensation capacitor. With this compensation scheme, the LDO can employ a multi-stage error amplifier for precise line and load regulation (total line and load error < 0.04%) without sacrificing chip area and its bandwidth. Thus, recovery time of LDO is 1 mus upon a step-load change in between 1 mA and 100 mA. Its output-capacitor-free nature and high area-efficiency make it particularly attractive for system-on-chip (SoC) designs. Proposed LDO is fabricated in a 0.35 mum standard CMOS technology and measurement results confirm with analysis and simulation results.

A novel three-stage CMOS operational amplifier (Op-amp) with high phase margin and high GBW is presented in this paper. The proposed Op-amp has the capability of driving large capacitive loads. Design of frequency compensation network for multistage CMOS Op-amp is always a big concern for researchers as design of compensation network is not quite simple and occupies large space on chip. Compensation network exploited exclusively for this Op-amp has an amalgamation of a very small valued single miller capacitor and differential amplifier and the network has been put in feed forward path. Use of smaller miller capacitor is preferred for low die area on chip and circuit complexity. All transistors of the proposed amplifier are biased by using supply voltage only without using any external current source. The simulated three stage Op-amp exhibits an open loop gain, the unity-gain bandwidth and phase margin as 122 dB, 2.77 MHz and 82.61&#x00B0; respectively. All simulations are done using 0.18 um technology with a 1.8V power supply.

A variable gain low noise amplifier (LNA) with low phase shift for a 38 GHz communication system of 5G application is presented in this paper. This design includes a 3-stage LNA and a 5-bit gain-controlled unit. Gm-boosting technique based on transformer is employed in the first stage to realize a good tradeoff between input match and noise figure (NF). Neutralized capacitors are utilized to improve the gain. The increased noise imported by neutralized capacitors is reduced by positive transformers. Gain-controlled unit is based on switched bridge-T/Pi attenuation structures. In order to reduce the phase shift, compensation capacitors are added in shunt branches of bridge-T/Pi attenuation units. The proposed design is fabricated in 65 nm CMOS process. It realizes a gain of 21 dB, NF of 4 dB and input 1dB compression point of −22 dBm at the maximum gain state. It has a gain-controlled range of 31 dB with 1 dB step. The root mean square (RMS) gain error is <0.8 dB and RMS phase shift is <5.4° from 33.5 GHz to 39 GHz. The chip size is 1.5 mm × 0.7 mm and power consumption is 28 mW with 1 V supply.

A three‐stage low‐noise amplifier (LNA) fabricated in a standard 0.18‐μm CMOS process (fT= 45 GHz) with a maximum gain of 18 dB at 23.2 GHz and a 5.8‐dB noise figure is presented. Parallel feedback between the gate and drain is used in all three stages. This configuration also provides much better linearity than other LNAs presented by resonating out the effect ofCgd. The amplifier has an output‐referred 3rd‐order intercept of 10 dBm, and a 3‐dB bandwidth of approximately 1 GHz. This paper demonstrates that parallel feedback is a viable technique for the design of 20+‐GHz CMOS LNAs. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 45: 309–312, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20806

In this paper, a three-stage class AB operational transconductance amplifier (OTA) with large slew rate is presented. The reversed nested Miller compensation technique is used to stabilize the proposed OTA, allowing the slew rate enhancement to be achieved by using class AB input and output stages. A flipped-voltage follower cell in the first stage in combination with a switched-capacitor level shifter in the last stage are utilized to implement the class AB operation. Circuit level simulation results are provided using HSPICE and a 90 nm CMOS technology which show 306 % enhancement in the large-signal FoM with approximately the same power dissipation compared to the class A OTA. The achieved settling time with 0.02 % accuracy for the proposed class AB and conventional class A OTAs are 7.5 and 15.3 ns, respectively.

A local active sub-threshold transconductance enhancement compensation technique is proposed for driving ultra-large capacitive loads (C L ). The sub-threshold transconductance enhancement compensation is used in outer loop of amplifier to enhance the cascode Miller compensation effect. At the same time, the local active compensation network is introduced to accurately eliminate the first pole-zero pair and improves the circuit stability. A new slew rate enhancement structure is also proposed, which can effectively increase the output swing. Implemented in standard 0.18-μm CMOS technology, proposed amplifier only consumes 41.27 μW of power at 1.2 V supply when driving a 20nF C L , achieving a gain-bandwidth product of 3.02 MHz, a phase margin of 69°, and an average slew rate of 0.09V/μs. The capacitance of compensation is only 475 fF, and the chip area of entire amplifier is 0.0043mm2.

A new pixel circuit is proposed for the realization of high resolution and high uniformity organic light-emitting diode on silicon (OLEDoS) microdisplays in this article. A compensation scheme is adopted to mitigate the influence of threshold voltage variation of the driving transistor on display uniformity. Furthermore, two coupling capacitors are used to reduce the voltage at the gate terminal of the driving transistor in order to extend the data voltage range. The performance of the proposed pixel circuit is verified in an industrial 0.18- $\mu \text{m}$ CMOS process. Simulation results show that the data voltage of the proposed pixel circuit ranges from 0.5 to 3.12 V, which is up to $4.37\times $ wider than the previously published pixel circuits. The emission current error of the proposed pixel circuit varies from −2.1% to 2.08%, under the condition of ±5 mV threshold voltage variation for the driving transistor. The maximum emission current error changes from −10.36% to −2.62% when the OLED turn-on voltage is increased by 5 to 20 mV due to device aging. Furthermore, the proposed pixel circuit only occupies a layout area of $8.1\,\,\mu \text{m}\,\,\times {4}\,\,\mu \text{m}$ .

An input-output rail-to-rail buffer amplifier is presented that is low noise, fast, and operates at ultra low currents. The amplifier targets energy harvesting applications that require low cost, high volume, and rugged manufacturing by avoiding use of non-standard device configurations or special processes. The main contributions of this work are: (1) The method of lowering voltage output noise by narrow-banding an amplifier, while introducing a time dependent bias current boost that is triggered by large differential input signals. Narrowbanding an amplifier to reduce its output noise, slows its dynamic response, and this method aims to restore and boost both the amplifier's slew rate and settling time. (2) Amplifier can operate at low VDD of about VGS+2VDS, while running in subthreshold, based in standard 0.18u digital CMOS. (3) PMOSFETs are utilized as inputs, compensation capacitors, and bias resistors in both the amplifier and the boost stages, which helps optimize for yield and lower noise. More importantly, the dynamic response of both the main amplifier and the boost stage being substantially dependent on PMOSFET device parameters, facilitates a smoother dynamic response in and out of boost, over process and operating variations. Based on montecarlo (MC) and worst case (WC) simulations, the following specifications are achievable: voltage output noise (VO nOiSe ) of 10 uv/Hz⁁1/2 at 1KHz, supply current (Idd) ∼ 500 nA; V dd minimum ∼0.6V; rail-to-rail voltage input (V IN ) range and output voltage (V OUT ) range of ∼ +/− 25mv from the rails; output resistor load (R l ) ∼2k Ohms; output capacitor load (C l ) ∼1nF; slew-rate (SR) −/+ ∼ 4/2.5 v/us; settling time (t S ) ∼ 5us to 1%; power supply rejection ratio (PSRR) −/+ ∼ 80dB/85dB, common mode rejection ration (CMRR) ∼ 125dB, unity gain bandwidth (f r ) ∼ 20KHz with phase margin (PM) ∼ 75 degrees; open loop gain (G) ∼ 85dB; preliminary area estimate of ∼ 180 um per side.

We present a compensation scheme with a damping circuit that automatically adjusts according to the load condition to overcome this problem and still maintain the power efficiency improvement over NMC. Capacitive loads as large as 20nF are used in some platforms for ESD protection and EMI suppression. Several compensation schemes for 3-stage amplifiers driving large capacitive loads with power efficiency more than 10 times that of the conventional nested Miller compensation (NMC) scheme have been reported recently.

This paper presents a novel 0.3V rail-to-rail body-driven three-stage operational transconductance amplifier (OTA). The proposed OTA architecture allows achieving high DC gain in spite of the bulk-driven input. This is due to the doubled body transconductance at the first and third stages, and to a high gain, gate-driven second stage. The bias current in each branch of the OTA is accurately set through gate-driven or bulk-driven current mirrors, thus guaranteeing an outstanding stability of main OTA performance parameters to PVT variations. In the first stage, the input signals drive the bulk terminals of both NMOS and PMOS transistors in a complementary fashion, allowing a rail-to-rail input common mode range (ICMR). The second stage is a gate-driven, complementary pseudo-differential stage with an high DC gain and a local CMFB. The third stage implements the differential-to-single-ended conversion through a body-driven complementary pseudo-differential pair and a gate-driven current mirror. Thanks to the adoption of two fully differential stages with common mode feedback (CMFB) loop, the common-mode rejection ratio (CMRR) in typical conditions is greatly improved with respect to other ultra-low-voltage (ULV) bulk-driven OTAs. The OTA has been fabricated in a commercial 130nm CMOS process from STMicroelectronics. Its area is about 0.002 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mm</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and power consumption is less than 35nW at the supply-voltage of 0.3V. With a load capacitance of 35pF, the OTA exhibits a DC gain and a unity-gain frequency of about 85dB and 10kHz, respectively.