Frequency-domain implementation of the transmitted-reference ultra-wideband receiver

Usage of digital receivers in today's radar and electronic warfare applications is becoming more common. Analog to digital converters (ADC) used in digital receivers play a significant role in the performance of these receivers. Therefore, it is very important to obtain performance analysis of possible ADC's under different conditions such as different temperature etc. before making final decision of the ADC to be used in the digital receiver. It is obvious that it would be very helpful to get results of integration of different ADC's with the existing system and to test ADC's under different conditions that may not exist on data sheets. For this reason, a Field Programmable Gate Array (FPGA) based board is designed in order to gather digital output of ADC being evaluated and a graphical analysis software responsible for analyzing gathered digital output is developed. Developed infrastructure enables us to compare performances of different ADC's in the same system and in same conditions by replacing only the ADC to be analyzed.

Recently, digital Intermediate Frequency (IF) waveform generators and receivers are introduced in modern radar systems to reduce the cost, size, and achieve better performance. Moreover, digital IF waveform generators achieve the requirements of high resolution and complex modulation schemes. Digital receivers have better sensitivity, wider dynamic range and lower noise Figure than analog receivers. Digital IF waveform generators and receivers work well in conjunction with a high-speed Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC). In this paper, the design and implementation of high-speed data acquisition circuits (ADC and DAC) to generate and acquire IF waveforms are presented. Different modulated waveforms are generated digitally using Field Programmable Gate Array (FPGA). The corresponding digital receiver, including digital phase detection and matched filtering, is designed and implemented on the same FPGA chip. Design and implementation of a Printed Circuit Board (PCB) including FPGA chip and its required circuitry are introduced. The proposed design is simulated using Computer-Aided Design (CAD) tools and verified experimentally through laboratory testing.

The burgeoning interest within the space community in digital beamforming is largely attributable to the superior flexibility that satellites with active antenna systems offer for a wide range of applications, notably in communication services. This paper delves into the analysis and practical implementation of a Digital Beamforming and Digital Down Conversion (DDC) chain, leveraging a high-speed Analog-to-Digital Converter (ADC) certified for space applications alongside a high-performance Field-Programmable Gate Array (FPGA). The proposed design strategy focuses on optimizing resource efficiency and minimizing power consumption by strategically sequencing the beamformer processor ahead of the complex down-conversion operation. This innovative approach entails the application of demodulation and low-pass filtering exclusively to the aggregated beam channel, culminating in a marked reduction in the requisite digital signal processing resources relative to traditional, more resource-intensive digital beamforming and DDC architectures. In the experimental validation, an evaluation board integrating a high-speed ADC and a FPGA was utilized. This setup facilitated the empirical validation of the design’s efficacy by applying various RF input signals to the digital beamforming receiver system. The ADC employed is capable of high-resolution signal processing, while the FPGA provides the necessary computational flexibility and speed for real-time digital signal processing tasks. The findings underscore the potential of this design to significantly enhance the efficiency and performance of digital beamforming systems in space applications.

Digital pulsed ultra wideband (UWB) receivers offer numerous advantages compared to architectures based on analogue correlation, but present unique implementation challenges. The specification of the Analogue-to-Digital Converter (ADC) resolution constitutes one of the most critical activities in the design of digital UWB receivers. Moreover, multi-bit ADCs must be associated with an Automatic Gain Control block which avoids the sub-optimal regimes of the ADC dominated by quantisation or saturation noise. This paper shows how to determine the ADC resolution requirements and the optimal Automatic Gain Control (AGC) settings for the general class of digital receivers. We conclude that 3 bits provide sufficient resolution on condition that the AGC scales the input signal at a reference root mean squared (RMS) level of half the ADC saturation voltage.

In this chapter, receiver sensitivity is discussed. The sensitivity of a receiver is defined as its ability to measure the weakest signal. The output of an analog-to-digital converter (ADC) is digital. This output impacts the measurement approach of input signals and thus receiver sensitivity. The conventional way to calculate sensitivity is through mathematical modeling. However, due to the nonlinear property ADCs, it is difficult to manipulate the calculations mathematically. As a result, the basic analysis is still based on an analog approach. If the ADC has a large number of bits, the result will be close to the analog approach. The threshold for detecting false alarms and signals in a digital receiver cannot be set arbitrarily in a continuous sense. The threshold can only be chosen from a finite number of levels. This chapter discusses different types of detection schemes. The difference between the detection schemes of analog and digital receivers is emphasized. The possible advantages of a digital receiver from a detection point of view are discussed. The detection based on one data sample is discussed first. The one-sample case is then extended to multiple samples. Finally, frequency domain detection, which can be applied to digital receivers, is examined. Examples with computer programs are used to illustrate some of the detection schemes. Before the general discussion, let us clarify the meaning of the word detection. This word has two distinct applications in a discussion of receivers. In the first sense, it refers to the process of converting a radio frequency (RF) signal or noise into a video signal. In the second sense, it refers to the process that determines whether a signal is present. In spite of this ambiguity, the meaning should be clear from the context.

in computer system, some digital display devices often are adopted. At this time if still select conventional analog interface, digital signal from person computer (PC) need be switched twice by D/A and A/D, lost of video signal will emerge, so a kind of new interface, DVI technology often need be studied. Combining with real project, this paper introduces the detailed developing methods of Digital Video Interface (DVI) transmitter and receiver in computer Systems. These include the arranging of the architecture of Digital Video Interface (DVI) transmitter and receiver, the design of over-sampler, elasticity buffer, clock recovery circuit, and data recovery circuits, in addition selecting and designing of Phase Frequency Detector (PFD), Charge Pump (CP) and Loop Filter (LF), and Voltage Controlled Oscillator (VCO) in hardware system were discussed in detail. These can offer a kind of reference method for developing of Digital Video Interface (DVI) transmitter and receiver hardware architecture in computer Systems.

The fundamental limits of communication over multiple-input multiple-output (MIMO) networks are considered when a limited number of one-bit analog to digital converters (ADC) are used at the receiver terminals. Prior works have mainly focused on point-to-point communications, where receiver architectures consisting of a concatenation of an analog processing module, a limited number of one-bit ADCs with non-adaptive thresholds, and a digital processing module are considered. In this work, a new receiver architecture is proposed which utilizes adaptive threshold one-bit ADCs - where the ADC thresholds at each channel-use are dependent on the channel outputs in the previous channel-uses - to mitigate the quantization rate-loss. Coding schemes are proposed for communication over the point-to-point and broadcast channels, and achievable rate regions are derived. In the high SNR regime, it is shown that using the proposed architectures and coding schemes leads to the largest achievable rate regions among all receiver architectures with the same number of one-bit ADCs.

Ultra-wideband (UWB) signals are widely used in radar, navigation and satellite communications. It is rather difficult to process UWB signals. In this paper we adopt dechirp pulse compression method to process the received UWB linear frequency modulated (LFM) signals. UWB signals are converted into signals with frequency components that are proportional to the relative range between the target and the reference target. It means to select low-speed analog-to-digital converters (ADC) for sampling UWB signals. The simulation results show that LFM signal with 600MHz center frequency, 200MHz bandwidth and 30usec pulse width can be processed under 70MHz sampling frequency by means of the method.

In this paper, we propose a low-complexity pseudo-de-quantization based (PDQ-based) iterative receiver in massive multi-user multi-input multi-output (MU-MIMO) systems with low resolution analog-to-digital converters (ADCs). First, a unified framework of massive MU-MIMO system with low resolution ADCs is presented. Then, a low-complexity iterative algorithm applying iterative soft decision interference cancellation (ISDIC) is introduced, where a soft information updating scheme is proposed for the PQD-based optimal detection and an iterative architecture of PDQ-based receiver is given. After that, the effect of quantization step size on the performance of PDQ-based iterative receiver is discussed and a new method is proposed to optimize the quantization step with given resolution ADCs. Finally, simulation results show that the PDQ-based iterative receiver can achieve significant improvement with iterative processing and provide a noticeable performance gain over the MMSE-ISDIC receiver with low resolution ADCs.

This paper presents a middleware design and architecture for hybrid digital cable receiver (HDCR) which provides both cable broadcast interface and broadband Ethernet interface, and is capable of handling mixed services efficiently including execution of interactive data application which is reusable from existing cable services based on OCAP.

In this paper, UWB direction finding technique using digital channelization receiver architecture Is proposed. The basic idea of this technique is to split the UWB array output into multiple frequency channels and then down-convert each channel into much lower frequency, hence allowing the low sampling rate ADC to be used. Estimation of the DoA of UWB source is achieved by forming a direction finding function using the spectral information from channelizer's output. A thorough performance analysis from simulation results is presented to verify the proposed technique and to investigate the effect of the system's parameters on the performance

Purpose – The purpose of this paper is to present a compressed sensing (CS)-based sampling system for ultra-wide-band (UWB) signal. By exploiting the sparsity of signal, this new sampling system can sub-Nyquist sample a multiband UWB signal, whose unknown frequency support occupies only a small portion of a wide spectrum. Design/methodology/approach – A random Rademacher sequence is used to sense the signal in the frequency domain, and a matrix constructed by Hadamard basis is used to compress the signal. The probability of reconstruction is proved mathematically, and the reconstruction matrix is developed in the frequency domain. Findings – Simulation results indicate that, with an ultra-low sampling rate, the proposed system can capture and reconstruct sparse multiband UWB signals with high probability. For sparse multiband UWB signals, the proposed system has potential to break through the Shannon theorem. Originality/value – Different from the traditional sub-Nyquist techniques, the proposed sampling system not only breaks through the limitation of Shannon theorem but also avoids the barrier of input bandwidth of analog-to-digital converters (ADCs).

In this paper, we derive the achievable rate of single-carrier frequency domain equalizer (SC-FDE) and orthogonal frequency division multiplexing (OFDM) systems, constrained on low resolution analog to digital converters (ADCs). We assume that there is a full knowledge of channels at both transmitter and receiver sides. We model low resolution ADCs with an additive uniform quantization noise. We consider an ultra-wide band millimeter wave (mm-Wave) system with a frequency selective channel. The channel is based on practical results at mm-Wave frequencies. Our numerical results show that SC-FDE systems with minimum mean square error (MMSE) equalizers outperform OFDM and SC-FDE systems with zero forcing (ZF) equalizers at high signal to noise ratio (SNR) regimes. Moreover, benefits of increasing the ADCs resolution are not significant due to exponentially increment in the power consumption of ADCs.

In the context of satellite-based positioning, the problem of range-estimation with low resolution analog-to-digital conversion (ADC) is considered. While ADC with coarse output resolution degrades the positioning performance of Global Navigation Satellite System (GNSS) receivers, it's simplicity allows to realize sampling at high spatial and temporal rates in an energy and hardware efficient way. Therefore, here the achievable range-estimation accuracy of GNSS receive systems with 1-bit ADC resolution, multiple antennas and high receive bandwidths is analyzed. For different scenarios, including multi-path propagation and the presence of broadband interference, we investigate the scaling behavior of the estimation performance when increasing the number of receive antennas or the sampling rate. Results for all considered scenarios show that if a moderately higher number of antennas or a moderately faster temporal rate is used, 1-bit GNSS receive systems have the potential to outperform ideal receivers with infinite ADC resolution. This insight emphasizes that a receiver architecture with 1-bit ADC has the potential to play an important role for future low-cost receivers as well as for sophisticated energy efficient high-performance GNSS systems.

This paper investigates the achievable uplink spectral efficiency (SE) of multi-cell massive multi-input multioutput (MIMO) systems with the low-resolution analog-to-digital converter (ADC) receiver architecture. For the maximum ratio combining detector, we derive an approximate expression for the achievable SE of the system, which enables the characterization of the impact of key system parameters such as transmit power, the number of antennas, and the ADC resolution bits on the achievable SE. Moreover, simple power scaling laws are presented.