Functional approaches to teaching concurrency

As products become ever more diversified, their life cycles are becoming shorter. To reduce production costs, increased process automation and concurrent design are priorities. Therefore, a collaborative integrated design system is crucial in the mold design and manufacturing process. This research develops a collaborative navigation system for concurrent mold design within the computer-aided design (CAD) browser, using Pro/Web.Link as the core tool. Providing both concurrent engineering and collaborative design functions, the navigation system is capable of assisting designers in accomplishing 3D mold development efficiently and accurately with the help of the standard component library and design decision-making system. The results show significant time savings over other mold design process methodologies.

The author demonstrates the natural extension of the box structure theory and techniques of system development to concurrent system design. The semantics and syntax of box structures for designing concurrency are presented. Concurrent box structure designs for several concurrent system environments are shown. Extensions to more complex environments are suggested. >

Orc was originally presented as a process calculus. It has now evolved into a full programming language, which we describe in this paper. The language has the structure and feel of a functional programming language, yet it handles many non-functional aspects effectively, including spawning of concurrent threads, time-outs and mutable state. We first describe the original concurrency combinators of the process calculus. Next we describe a small functional programming language that forms the core language. Then we show how the concurrency combinators of the process calculus and the functional core language are integrated seamlessly. The resulting language and its supporting libraries have proven very effective in describing typical concurrent computations; we demonstrate how several practical concurrent programming problems are easily solved in Orc.KeywordsConcurrent ProgrammingMeeting TimeSite CallProcess CalculusConcurrent ThreadThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Originally published in IEEE Transactions on Components and Packaging Technology Vol. 20 No. 2. IEEE holds all copyright of this article. IEEE allows the final published version of author's own work to be deposited in institutional repositories.

Process-oriented design and implementation of concurrent systems has important benefits. However, the inherent complexity of concurrent processes’ communication imposes challenges such as verifying consistency between the process-oriented design and implementation of a concurrent system. To deal with such a challenge, we use Galois connections, Failures and Category Theory to construct a formal framework for designing, implementing, analyzing and verifying consistency of concurrent systems. For the purpose of illustrating the framework, a running concurrent system is designed by Communicating Sequential Processes, implemented by a process-oriented programming language Erasmus.

Ordered Binary-Decision Diagrams (OBDD) are the state-of-the art<br />data structure for boolean function manipulation and there exist<br />several software packages for OBDD manipulation. OBDDs have<br />been successfully used to solve problems in e.g. digital-systems design, verification and testing, in mathematical logic, concurrent system design and in artificial intelligence. The OBDDs used in many of these applications quickly get larger than the available main memory and it becomes essential to consider the problem of minimizing the Input/Output (I/O) communication. In this paper we analyze why existing OBDD manipulation algorithms perform poorly in an I/O environment and develop new I/O-efficient algorithms.

Process algebra provides essential tools for studying concurrent systems. An important branch of process algebra is value passing CCS. However, value passing CCS lacks not only action refinement, which is an essential operation in the design of concurrent systems, but also non-interleaving semantics, which is appropriate to specify the partial order and equivalence relations. In this paper, we will define action refinement and non-interleaving semantics by valued stable event structures and valued labeled configuration structures in which special valued actions will be executed. The refinement operation and semantics are useful for the hierarchical design methodology in value passing CCS, e.g. top-down system design.

A race condition is a situation where two threads manipulate a data structure simultaneously, without synchronization. Race conditions are common errors in multithreaded programming. They often lead to unintended nondeterminism and wrong results. Moreover, they are notoriously hard to diagnose, and attempts to eliminate them can introduce deadlocks. In practice, race conditions and deadlocks are often avoided through prudent programming discipline: protecting each shared data structure with a lock and imposing a partial order on lock acquisitions. In this paper we show that this discipline can be captured (if not completely, to a significant extent) through a set of static rules. We present these rules as a type system for a concurrent, imperative language. Although weaker than a full-blown program-verification calculus, the type system is effective and easy to apply. We emphasize a core, first-order type system focused on race conditions; we also consider extensions with polymorphism, existential types, and a partial order on lock types.KeywordsType SystemOperational SemanticCritical SectionReference CellRace ConditionThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Using Failures and Category Theory to Verify Process Communications between Design and Implementation of Concurrent Systems

Space science mission concurrent design is to meet the scientific mission requirements, optimize the spacecraft design and ultimately reaches a feasible solution for the proposed program. The information management system for space science mission concurrent design is developed to manage all design disciplinary data and support data exchange between the coupled disciplines. The space science mission concurrent design process and information involved are reviewed and analyzed. The system architecture is divided into three layers, including the data persistence layer, business logic layer and presentation layers. Data persistence layer provides local data services, data entities access, data entities, file system. Business logic layer provides file management, workflow management and data exchange interface. Presentation layer provides interactive interface. A space science mission application is given as an example. The simulation results show the mission design can be performed via the information management system to acquire high quality results.

This paper studies the problem of verifying linearizability at runtime, where one seeks for a concurrent algorithm for verifying that the current execution of a given concurrent shared object implementation is linearizable. It shows that it is impossible to runtime verify linearizability for some common sequential objects, regardless of the consensus power of base objects. Then, it argues that actually a stronger version of the problem can be solved, if linearizability is verified indirectly. Namely, it shows that (1) linearizability of a class of concurrent implementations can be strongly verified using only read/write base objects (i.e. without the need of consensus), and (2) any implementation can be transformed to its counterpart in the class (which implements the same object) using only read/write objects too. As far as we know, this is the first runtime verification algorithm for any correctness condition that is fully asynchronous and fault-tolerant. As a by-product, a simple and generic methodology for deriving self-enforced linearizable implementations is obtained. This type implementations produce outputs that are guaranteed linearizable, and are able to produce a certificate of it, which allows the design of concurrent systems in a modular manner with accountable and forensic guarantees. These results hold not only for linearizability but for a correctness condition that includes generalizations of it such as set-linearizability and interval-linearizability.

PN (PN) are tools for the analysis and design of concurrent systems. There is a formal theory, which supports PN. An extension of PN is Petri Nets with Clocks (PNwC). PNwC are useful to model systems with temporal requirements via specification of clocks, using temporal invariants for the places and temporal conditions in the transitions. Using invariants in places allows the specifications of hard deadlines constrains (upper bound constrains): when a deadline is reached the progress of time is blocked by the invariant and the action becomes urgent. An algorithm for the analysis of a PNwC has been proposed in [1]. The algorithm is oriented to the verification and correction of errors in the modelling of the time variable. The algorithm generates information about temporal unreachable states and process deadlocks with temporal blocks. Also, it corrects places invariants and transitions conditions. We present here a formalism for PNwC based on Timed Graphs. The analysis algorithm is presented here using the formalism. We show here how Petri Net theory can be joined with Timed Graph theory to construct a formalism, which supports a tool for the analysis of models of concurrent process with real time specification.

As critical computer systems continue to grow in complexity, the task of showing that they execute correctly becomes more difficult. For this reason, research in software engineering has turned to formal methods, i.e., rigorous approaches to demonstrating the correctness of software systems. Unfortunately, the formal methods currently used in the design of concurrent systems do not provide any mechanisms for specifying and reasoning about the mapping of software to hardware. As a result, architectural constraints, even though they play an important role in the design process, are left out of the formal framework. We show how to state architectural constraints in a formal notation, how to prove that programs are allocated correctly to the underlying architecture, and how to factor architectural considerations into a program derivation process which uses a mixture of specification and program refinements. The approach is illustrated by the derivation of two related programs that solve the same problem but are designed to work on distinct architectures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An asynchronous Low Voltage Detect (LVD) interrupt during the self-test portion of the reset sequence of a microcontroller randomly caused a corrupted clock state that was not recoverable except through a power on reset, or POR. This paper discusses the techniques used to overcome the many obstacles encountered to determine the root cause of the race condition that corrupted the clock state machine registers.

Program testing is the most widely adopted approach for assuring the quality and reliability of software systems. Despite the popularity of the objected-oriented programs, its testing is much more challenging than that of the conventional programs. We proposed previously a methodology known as TACCLE for testing object-oriented software. It has not, however, addressed the aspects of concurrency and non-determinism. In this paper, we propose a scheme for dynamically detecting and testing concurrency in object-oriented software by executing selected concurrent pairs of operations. The scheme is based on OBJSA nets and addresses concurrency and nondeterminism problems. An experimental case study is reported to show the effectiveness of the scheme in detecting deadlocks, race conditions and other coherence problems. The scheme supplements our previous static approach to detecting deadlock in Java multithreaded programs.