Generalized reasoning scheme for redundancy addition and removal logic optimization

Redundancy addition and removal (RAR) uses automatic test pattern generation (ATPG) techniques to identify logic optimization transforms. It has been applied successfully to combinational and sequential logic optimization and to layout driven logic synthesis for FPGAs. We present an improved RAR technique that allows to one to identify new types of optimization transforms and it is more efficient because it reduces the number of ATPG runs required. Also, we apply the RAR method to timing optimization. The experimental results show that this improved RAR technique produces significant timing optimization with very little area cost.

Redundancy Addition and Removal (RAR) and ATPG/Diagnosis-based Design Rewiring (ADDR) are both logic restructuring techniques used in the synthesis and optimization of logic designs. However, not every irredundant target wire can be successfully removed due to some limitations in these two approaches. Therefore, this paper proposes an efficient restructuring technique, Error Injection & Correction (EIC), which formally constructs a corresponding rectification network at feasible locations without verification efforts for the injected errors of the wire removal, addition, or gate replacement. We use the EIC to serve as a logic perturbation engine and combine other logic optimization engines to optimize the circuit. The experimental results show that the size of highly optimized circuits can be further reduced with this EIC technique as compared with the configuration using only logic optimization engines.

The paper attempts to determine the capabilities of existing redundancy addition and removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we compare this method with the retiming and resynthesis (RaR) techniques. For the RaR case the set of possible transformations has been established by relating them to STG transformations by other authors. Following these works, we first formally demonstrate that logic transformations provided by RaR are covered by SRAR as well. Then we also show that SRAR is able to identify transformations that cannot be found by RaR. This way we prove the higher potential of the sequential redundancy addition and removal over the retiming and resynthesis techniques.

In this paper, we propose a layout driven synthesis approach for Field Programmable Gate Arrays (FPGAs). The approach attempts to identify alternative wires and alternative functions for wires that cannot be routed due to the limited routing resources in FPGA. The alternative wires (in the logic level) that can be routed through less congested areas substitute the unroutable wires without changing the circuit's functionality. Allowing the logic blocks to have alternative functions also increases the flexibility of routing. The redundancy addition and removal techniques are used to identify such alternative wires. Experimental results are presented to demonstrate the usefulness of this approach. For a set of randomly selected benchmark circuits, on the average, 30%-50% of wires have alternative wires. These results indicate that the routing flexibility can be substantially increased by considering these alternative wires. Our prototype system successfully completed the routing for two AT&T designs that cannot be handled by an FPGA router alone. The proposed synthesis technique can also be applied to standard cell and gate array designs to reduce the routing area.

Redundancy addition and removal, also known as rewiring, is a building block of a wide range of circuit optimization applications. In this paper, we propose a novel improvement on the FIRE redundancy identification technique and augment the state-of-the-art rewiring scheme RAMFIRE with it. Our method increases the number of alternative wires identified by 10% and improves the runtime by nearly 20%. Optimization applications based on rewiring can take the advantage of this speed up and enhanced rewiring power.

Non-additive image steganographic framework based on variational inference in Markov Random Fields

The paper deals with logic synthesis of lookup-table (LUT) based field-programmable gate arrays (FPGAs). Because each LUT can implement any k input Boolean function with the same area cost, the optimisation criterion of literal count, generally used in other multi-level logic synthesis methods, is not suitable for LUT-based technologies. Therefore a new logic optimisation criterion is proposed, which trades off literals against support. Based on this criterion, five logic operations in logic optimisation are analysed, and made to evaluate the circuit cost in accordance with the target technology. Using these techniques of logic optimisation, a good starting point for technology mapping of LUT-based FPGAs has been obtained. In the technology mapping phase, LUT-directed decomposition is applied. Experimental results indicate that synthesised circuits are much smaller and more routable than the circuits synthesised by other tools.

Client-Agent-Server model (CAS model) which can decrease the work load of the client by adding agent processors to the Client-Server model (CS model) is proposed and an approach to parallel test generation for logic circuits on the CAS model is presented. Two problems are considered: optimal granularity problem and optimal scheme problem. First, the problem of parallel test generation on the CAS model is formulated to analyze the effect of the granularity (grain size of target faults allocated to processors) in both cases of static and dynamic task allocation (optimal granularity problem). Then the relationship between the number of processors and the total processing time is analyzed (optimal scheme problem). From the analysis, it is shown that the CAS model can reduce the total processing time over the CS model and that there exists an optimal scheme (an optimal pair of numbers of agent processors and server processors) for the CAS model which minimizes the total processing time for a given number of processors. To corroborate the analysis, the proposed parallel test generation algorithm is implemented on a network of more than 100 workstations and experimental results for the ISCAS benchmark circuits are presented. It is shown that the experimental results are very close to the theoretical results which confirms the existence of optimal granularity and optimal scheme which minimizes the total processing time for the CAS model. >

The paper considers discrete multitone (DMT) modulation for multiuser communications when multiple users are supported by the same system, a zero-padding redundancy is employed at the transmitter output, and linear redundancy removal is used at the channel output. These users may have differing quality of service (QoS) requirements, as quantified by bit rate and symbol-error rate specifications, and are each assigned an equal number of subchannels. Our goal is to minimize the transmitted power, given the QoS specifications and subject to the knowledge of the channel and the second-order statistics of the colored interference at the receiver input. In particular, we find an optimum bit-loading scheme that distributes the bit rate transmitted across the various subchannels belonging to each user, and, subject to this bit allocation, we determine the precise subchannels assigned to each user, the optimum transceiver characterized by the input/output block transforms, and the redundancy removal operation. A major conclusion is that even though the optimum bit-rate allocation differs from the single-user case, the optimum transceiver does not. Further, it is determined entirely by the channel and interference conditions, and is unaffected by the QoS requirements.

This paper addresses SAT-based Unbounded Model Checking based on Craig Interpolants. This recently introduced methodology is often able to outperform BDDs and other SAT-based techniques on large verification instances. Based on refutation proofs generated by SAT solvers, interpolants provide compact circuit representations of state sets, and abstract away several details non relevant for proofs. We propose three main contributions, aimed at controlling interpolant size and traversal depth. First of all, we introduce interpolant-based dynamic abstraction to reduce the support of the computed interpolant. Second, we propose new advances in interpolant compaction by redundancy removal. Both techniques rely on an effective application of the incremental SAT paradigm. Finally, we also introduce interpolant computation exploiting circuit quantification, instead of SAT refutation proofs. Experimental results are specifically oriented to prove properties, rather than disproving them (bug hunting). They show how the methodology is able to extend the applicability of interpolant based Model Checking to larger and deeper verification instances.

We consider the task of document-level entity linking (EL), where it is important to make consistent decisions for entity mentions over the full document jointly. We aim to leverage explicit “connections” among mentions within the document itself: we propose to join EL and coreference resolution (coref) in a single structured prediction task over directed trees and use a globally normalized model to solve it. This contrasts with related works where two separate models are trained for each of the tasks and additional logic is required to merge the outputs. Experimental results on two datasets show a boost of up to +5% F1-score on both coref and EL tasks, compared to their standalone counterparts. For a subset of hard cases, with individual mentions lacking the correct EL in their candidate entity list, we obtain a +50% increase in accuracy.

In this paper, an optimal control scheme for reducing the fluctuation of residual gas fraction (RGF) under variational operating condition is developed by combining stochastic logical system approach with statistical learning method. The method estimating RGF from measured in-cylinder pressure is introduced firstly. Then, the stochastic properties of the RGF are analyzed according to statistical data captured by conducting experiments on a test bench equipped with a L4 internal combustion engine. The influences to the probability distribution of the RGF from both control input and environment parameters are also analyzed. Based on the statistical analysis, a stochastic logical transient model is adopted for describing cyclic behavior of the RGF. Optimal control policy maps for different fixed operating conditions are calculated then. Besides, a statistical learning-based method is applied to learn the probability density function (PDF) of RGF in the real-time which is used to adjust the control MAP based on logical optimization. The whole optimal control policy map is obtained based on Gaussian process regression with consideration of statistical information of RGF. Finally, the performance of the proposed method is experimentally validated.

This paper introduces techniques from combinatorial and algebraic topology to help in explaining and measuring the performance of modern logic minimizers. The concepts of simple and the Euler-Poincare characteristic of a logic cover are defined and analyzed. In particular, simple is related to the minimization algorithms Espresso-EXACT and Roth's Extraction Algorithm. Experimental results on the Euler-Poincare characteristic, along with a new measure, the Euler Ratio are related to the function complexity concepts of cyclic constraints in Espresso_EXACT, the CyclicKernel in Roth's Extraction Algorithm, and cubical homotopy introduced in this paper.

Logical query optimization for Cloudera Impala system

We propose in this paper a variable-coefficient fixed-length (VCFL) coding scheme for wavelet-based image transmission over noisy channels. When an image is transmitted through noisy channel with high throughput, both image compression and error-resistant coding scheme need to be considered. In this approach, an image is first decomposed into subbands by wavelet transform and quantized using an adaptive quantization scheme. The adaptive quantization is adaptive to both the frequency characteristics and the spatial constraints based on Gibbs random field. The traditional variable length entropy coding schemes, such as Huffman coding or arithmetic coding, and the fixed length coding such as LZW are usually very sensitive to channel noise for image transmission applications. Even with the insertion of synchronization symbols, they still cannot be directly employed without additional error correction/detection coding. To overcome the difficulty of image transmission over noisy channels, we propose to code the quantized subband coefficients with the VCFL scheme. This coding scheme attempts to keep the balance between redundancy removal, synchronization detection and error resilience. Part of the codebook is field based on the observation of the coefficient spatial distribution patterns in each subbands to alleviate the transmission of the codebook. The remaining code positions within the fixed length codebook can be utilized to combat channel errors by carefully arranging the code positions such that the codes with biggest transition cost will have the biggest Hamming distance. These positions can laos be filled with other frequently appeared coefficient composition sequences to achieve higher compression ratio. Experimental results of image transmission over noisy channels are reported to show the promising potential of the proposed coding scheme.